diff options
Diffstat (limited to 'src/soc/intel/apollolake')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 956a55b4a7..5f9b346cc3 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -622,7 +622,7 @@ static void glk_fsp_silicon_init_params_cb( /* * Options to adjust PMIC Vdd2 voltage. */ - silconfig->PmicVdd2Voltage = cfg->PmicVdd2Voltage; + silconfig->PmicVdd2Voltage = cfg->pmic_vdd2_voltage; /* FSP should let coreboot set subsystem IDs, which are read/write-once */ silconfig->SiSVID = 0; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 5a3aa880c5..2d6b07929d 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -204,7 +204,7 @@ struct soc_intel_apollolake_config { * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]: * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default). */ - uint32_t PmicVdd2Voltage; + uint32_t pmic_vdd2_voltage; /* Option to enable VTD feature. Default is 0 which disables VTD * capability in FSP. Setting this option to 1 in devicetree will enable |