1 files changed, 8 insertions, 29 deletions
diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c
index 0a32b715b0..311e580636 100644
--- a/src/soc/intel/apollolake/uart_early.c
+++ b/src/soc/intel/apollolake/uart_early.c
@@ -17,7 +17,7 @@
 
 #include <console/uart.h>
 #include <device/pci.h>
-#include <intelblocks/lpss.h>
+#include <intelblocks/uart.h>
 #include <soc/gpio.h>
 #include <soc/uart.h>
 #include <soc/pci_devs.h>
@@ -31,32 +31,6 @@ static inline int invalid_uart_for_console(void)
 	return 0;
 }
 
-void lpss_console_uart_init(void)
-{
-	uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
-	device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
-
-	if (invalid_uart_for_console())
-		return;
-
-	/* Enable BAR0 for the UART -- this is where the 8250 registers hide */
-	pci_write_config32(uart, PCI_BASE_ADDRESS_0, base);
-
-	/* Enable memory access and bus master */
-	pci_write_config32(uart, PCI_COMMAND,
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
-	/* Take UART out of reset */
-	lpss_reset_release(base);
-
-	/*
-	 * Set M and N divisor inputs and enable clock. These values
-	 * get us a 1.836 MHz clock (ideally we want 1.843 MHz)
-	 */
-	lpss_clk_update(base, 0x025a, 0x7fff);
-
-}
-
 uintptr_t uart_platform_base(int idx)
 {
 	return CONFIG_CONSOLE_UART_BASE_ADDRESS;
@@ -69,8 +43,11 @@ static const struct pad_config uart_gpios[] = {
 	PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1),		/* UART2 TX */
 };
 
-void soc_console_uart_init(void)
+void pch_uart_init(void)
 {
+	uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+	device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
+
 	/* Get a 0-based pad index. See invalid_uart_for_console() above. */
 	const int pad_index = CONFIG_UART_FOR_CONSOLE - 1;
 
@@ -80,5 +57,7 @@ void soc_console_uart_init(void)
 	/* Configure the 2 pads per UART. */
 	gpio_configure_pads(&uart_gpios[pad_index * 2], 2);
 
-	lpss_console_uart_init();
+	/* Program UART2 BAR0, command, reset and clock register */
+	uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL);
+
 }