diff options
Diffstat (limited to 'src/soc/intel/apollolake/memmap.c')
| -rw-r--r-- | src/soc/intel/apollolake/memmap.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 8b51a85b76..bda43bbdbf 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -15,9 +15,11 @@ * GNU General Public License for more details. */ +#include <arch/romstage.h> #include <assert.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <device/pci.h> #include <soc/systemagent.h> @@ -47,3 +49,31 @@ void smm_region(uintptr_t *start, size_t *size) *start = sa_get_tseg_base(); *size = sa_get_tseg_size(); } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + uintptr_t top_of_ram; + uintptr_t smm_base; + size_t smm_size; + + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + /* cbmem_top() needs to be at least 16 MiB aligned */ + assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); + postcar_frame_add_mtrr(pcf, top_of_ram - 16*MiB, 16*MiB, + MTRR_TYPE_WRBACK); + + /* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); +} |