diff options
Diffstat (limited to 'src/soc/intel/apollolake/lpc.c')
| -rw-r--r-- | src/soc/intel/apollolake/lpc.c | 41 |
1 files changed, 0 insertions, 41 deletions
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 06ca0db7b1..10677df503 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -20,46 +20,6 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/pci_ids.h> -#include <reg_script.h> -#include <vendorcode/google/chromeos/chromeos.h> -#include <soc/lpc.h> -#include "chip.h" - -static const struct reg_script lpc_serirq_enable[] = { - /* Setup SERIRQ, enable continuous mode */ - REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), -#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) - REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), -#endif - REG_SCRIPT_END -}; - -static void enable_lpc_decode(struct device *lpc) -{ - const struct soc_intel_apollolake_config *config; - - if (!lpc || !lpc->chip_info) - return; - - config = lpc->chip_info; - - /* Enable requested fixed IO decode ranges */ - pci_write_config16(lpc, LPC_EN, config->lpc_dec); - - /* Enable generic IO decode ranges */ - pci_write_config32(lpc, LPC_GEN1_DEC, config->gen1_dec); - pci_write_config32(lpc, LPC_GEN2_DEC, config->gen2_dec); - pci_write_config32(lpc, LPC_GEN3_DEC, config->gen3_dec); - pci_write_config32(lpc, LPC_GEN4_DEC, config->gen4_dec); -} - - -static void lpc_init(struct device *dev) -{ - enable_lpc_decode(dev); - reg_script_run_on_dev(dev, lpc_serirq_enable); -} - static void soc_lpc_add_io_resources(device_t dev) { @@ -87,7 +47,6 @@ static struct device_operations device_ops = { .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, - .init = &lpc_init }; static const struct pci_driver soc_lpc __pci_driver = { |