diff options
Diffstat (limited to 'src/soc/intel/apollolake/chip.c')
| -rw-r--r-- | src/soc/intel/apollolake/chip.c | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 1075642517..c4e068d41f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -99,6 +99,10 @@ /* IOSF Gasket Backbone Local Clock Gating Enable */ #define IOSFGBLCGE (1 << 0) +#define CFG_XHCPMCTRL 0x80a4 +/* BIT[7:4] LFPS periodic sampling for USB3 Ports */ +#define LFPS_PM_DISABLE_MASK 0xFFFFFF0F + const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) @@ -829,6 +833,30 @@ static int check_xdci_enable(void) return !!dev->enabled; } +static void disable_xhci_lfps_pm(void) +{ + struct soc_intel_apollolake_config *cfg; + + cfg = config_of_soc(); + + if (cfg->disable_xhci_lfps_pm) { + void *addr; + const struct resource *res; + uint32_t reg; + struct device *xhci_dev = PCH_DEV_XHCI; + + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + addr = (void *)(uintptr_t)(res->base + CFG_XHCPMCTRL); + reg = read32(addr); + printk(BIOS_DEBUG, "XHCI PM: control reg=0x%x.\n", reg); + if (reg) { + reg &= LFPS_PM_DISABLE_MASK; + write32(addr, reg); + printk(BIOS_INFO, "XHCI PM: Disable xHCI LFPS as configured in devicetree.\n"); + } + } +} + void platform_fsp_notify_status(enum fsp_notify_phase phase) { if (phase == END_OF_FIRMWARE) { @@ -876,6 +904,9 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) IOSFGBLCGE; write32(cfg, reg); } + + /* Disable XHCI LFPS power management if the option in dev tree is set. */ + disable_xhci_lfps_pm(); } } |