diff options
Diffstat (limited to 'src/soc/intel/apollolake/acpi')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/globalnvs.asl | 5 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/northbridge.asl | 25 |
2 files changed, 16 insertions, 14 deletions
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 4aad29c81a..1db373d484 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2020 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -45,6 +45,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve) EPCS, 8, // 0x2C - SGX Enabled status EMNA, 64, // 0x2D - 0x34 EPC base address ELNG, 64, // 0x35 - 0x3C EPC Length + E4GM, 8, // 0x3D - Enable above 4GB MMIO Resource + A4GB, 64, // 0x3E - 0x45 Base of above 4GB MMIO Resource + A4GS, 64, // 0x46 - 0x4D Length of above 4GB MMIO Resource /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 027e2a623c..ff146ec9db 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2020 Intel Corp. * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#define BASE_64GB 0x1000000000 Name(_HID, EISAID("PNP0A08")) /* PCIe */ Name(_CID, EISAID("PNP0A03")) /* PCI */ @@ -115,18 +114,18 @@ Method (_CRS, 0, Serialized) Add(Subtract(GMAX, GMIN), 1, GLEN) /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) - - Store (\_SB.PCI0.MCHC.TUUD, Local0) - - If (LLessEqual (Local0, BASE_64GB)) - { - Store (0, MMIN) - Store (0, MLEN) + If (LEqual (A4GS, 0)) { + CreateQwordField (MCRS, PM02._LEN, MSEN) + Store (0, MSEN) + } Else { + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) + /* Set 64bit MMIO resource base and length */ + Store (A4GS, MLEN) + Store (A4GB, MMIN) + Subtract (Add (MMIN, MLEN), 1, MMAX) } - Subtract (Add (MMIN, MLEN), 1, MMAX) Return (MCRS) } |