diff options
Diffstat (limited to 'src/soc/intel/apollolake/acpi/xhci.asl')
| -rw-r--r-- | src/soc/intel/apollolake/acpi/xhci.asl | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl new file mode 100644 index 0000000000..fc67074a8a --- /dev/null +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -0,0 +1,41 @@ +/* This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* XHCI Controller 0:15.0 */ +Device(XHC1) { + Name(_ADR, 0x00150000) // Device 21, Function 0 + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + // Declare XHCI GPE status and enable bits are bit 13 + Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) + + Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake + { + Return (Zero) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Method(_STA, 0) + { + Return (0xF) + } + +} |