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-rw-r--r--src/soc/intel/alderlake/espi.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c
index b2377274e5..b489ef6a15 100644
--- a/src/soc/intel/alderlake/espi.c
+++ b/src/soc/intel/alderlake/espi.c
@@ -20,21 +20,6 @@
#include <soc/pcr_ids.h>
#include <soc/soc_chip.h>
-/*
-* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
-* certain memory range as reserved range for BIOS usage.
-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
-*/
-static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = {
- { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
- { 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
-{
- return lpc_fixed_mmio_ranges;
-}
-
void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
{
const config_t *config = config_of_soc();