diff options
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/pch.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/espi.c | 9 |
2 files changed, 2 insertions, 25 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 528e4de46e..662f33e1b7 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -40,9 +40,6 @@ #define PCR_DMI_PMBASEA 0x27AC #define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static void soc_config_pwrmbase(void) { /* @@ -123,19 +120,8 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) { - io_enables = lpc_enable_fixed_io_ranges(io_enables); - /* - * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same - * value programmed in ESPI PCI offset 82h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); - /* - * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same - * value programmed in LPC PCI offset 80h. - */ - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); - } + if (pch_check_decode_enable() == 0) + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index b489ef6a15..feec465a92 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -30,15 +30,6 @@ void soc_get_gen_io_dec_range(uint32_t *gen_io_dec) gen_io_dec[3] = config->gen4_dec; } -void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) -{ - /* Mirror these same settings in DMI PCR */ - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); -} - #if ENV_RAMSTAGE void lpc_soc_init(struct device *dev) { |