diff options
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/pcie_rp.c | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/pcie_rp.c b/src/soc/intel/alderlake/pcie_rp.c index dd0cfbc637..26ce785e8e 100644 --- a/src/soc/intel/alderlake/pcie_rp.c +++ b/src/soc/intel/alderlake/pcie_rp.c @@ -6,6 +6,8 @@ #include <soc/pci_devs.h> #include <soc/pcie.h> +#define CPU_CPIE_VW_IDX_BASE 24 + static const struct pcie_rp_group pch_lp_rp_groups[] = { { .slot = PCH_DEV_SLOT_PCIE, .count = 8 }, { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4 }, @@ -91,3 +93,20 @@ enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) return PCIE_RP_UNKNOWN; } + +int soc_get_cpu_rp_vw_idx(const struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return -1; + + switch (dev->path.pci.devfn) { + case SA_DEVFN_CPU_PCIE1_0: + return CPU_CPIE_VW_IDX_BASE; + case SA_DEVFN_CPU_PCIE6_0: + return CPU_CPIE_VW_IDX_BASE + 3; + case SA_DEVFN_CPU_PCIE6_2: + return CPU_CPIE_VW_IDX_BASE + 2; + default: + return -1; + } +} |