diff options
Diffstat (limited to 'src/soc/intel/alderlake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 7e842a200c..a615f0bc6a 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -41,8 +41,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Set CpuRatio to match existing MSR value */ m_cfg->CpuRatio = (rdmsr(MSR_FLEX_RATIO).lo >> 8) & 0xff; - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) + for (i = 0; i < ARRAY_SIZE(config->PchPcieRpEnable); i++) { + if (config->PchPcieRpEnable[i]) mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; @@ -155,9 +155,12 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Skip CPU replacement check */ m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck; - /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ - dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); - m_cfg->CpuPcieRpEnableMask = is_dev_enabled(dev); + mask = 0; + for (i = 0; i < ARRAY_SIZE(config->CpuPcieRpEnable); i++) { + if (config->CpuPcieRpEnable[i]) + mask |= (1 << i); + } + m_cfg->CpuPcieRpEnableMask = mask; m_cfg->TmeEnable = CONFIG(INTEL_TME); |