diff options
Diffstat (limited to 'src/soc/intel/alderlake/chip.h')
| -rw-r--r-- | src/soc/intel/alderlake/chip.h | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 38d9671f60..8e59c9ad5c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -118,9 +118,12 @@ struct soc_intel_alderlake_config { uint8_t PchHdaIDispLinkFrequency; uint8_t PchHdaIDispCodecDisconnect; - /* PCIe Root Ports */ - uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* CPU PCIe Root Ports */ + uint8_t CpuPcieRpEnable[CONFIG_MAX_CPU_ROOT_PORTS]; + + /* PCH PCIe Root Ports */ + uint8_t PchPcieRpEnable[CONFIG_MAX_PCH_ROOT_PORTS]; + uint8_t PcieRpHotPlug[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ @@ -130,7 +133,7 @@ struct soc_intel_alderlake_config { uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ - uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe RP L1 substate */ enum L1_substates_control { @@ -138,13 +141,13 @@ struct soc_intel_alderlake_config { L1_SS_DISABLED, L1_SS_L1_1, L1_SS_L1_2, - } PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + } PcieRpL1Substates[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIe LTR: Enable (1) / Disable (0) */ - uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpLtrEnable[CONFIG_MAX_PCH_ROOT_PORTS]; /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ - uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_PCH_ROOT_PORTS]; /* Gfx related */ enum { |