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Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 5b624d8ae1..5f24e37036 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -252,8 +252,8 @@ config MAX_PCIE_CLOCK_SRC int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N - default 18 if SOC_INTEL_ALDERLAKE_PCH_S default 10 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S help With external clock buffer, Alderlake-P can support up to three additional source clocks. This is done by setting the corresponding GPIO pin(s) to native function to use as |