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-rw-r--r--src/soc/imgtec/pistachio/include/soc/memlayout.ld2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
index edf9c41493..a0b48b2e6d 100644
--- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld
+++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld
@@ -29,6 +29,8 @@ SECTIONS
POSTRAM_CBFS_CACHE(0x00200000, 512K)
RAMSTAGE(0x00280000, 128K)
+ /* 0x18100000 -> 0x18540000 */
+ SOC_REGISTERS(0x18100000, 0x440000)
/*
* GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock
* and then through the identity mapping in ROM stage.