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Diffstat (limited to 'src/soc/cavium/cn81xx/include')
-rw-r--r--src/soc/cavium/cn81xx/include/soc/addressmap.h1
-rw-r--r--src/soc/cavium/cn81xx/include/soc/memlayout.ld6
2 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/cavium/cn81xx/include/soc/addressmap.h b/src/soc/cavium/cn81xx/include/soc/addressmap.h
index f6983064fc..f188961930 100644
--- a/src/soc/cavium/cn81xx/include/soc/addressmap.h
+++ b/src/soc/cavium/cn81xx/include/soc/addressmap.h
@@ -62,6 +62,7 @@
/* RST */
#define RST_PF_BAR0 (0x87E006000000ULL + 0x1600)
+#define RST_SOFT_RESET (RST_PF_BAR0 + 0x80ULL)
#define RST_PP_AVAILABLE (RST_PF_BAR0 + 0x138ULL)
#define RST_PP_RESET (RST_PF_BAR0 + 0x140ULL)
#define RST_PP_PENDING (RST_PF_BAR0 + 0x148ULL)
diff --git a/src/soc/cavium/cn81xx/include/soc/memlayout.ld b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
index b80d152f97..e3bf61f1f4 100644
--- a/src/soc/cavium/cn81xx/include/soc/memlayout.ld
+++ b/src/soc/cavium/cn81xx/include/soc/memlayout.ld
@@ -28,14 +28,18 @@ SECTIONS
/* Insecure region 1MiB - TOP OF DRAM */
/* bootblock-custom.S does setup CAR from SRAM_START to SRAM_END */
SRAM_START(BOOTROM_OFFSET)
+
STACK(BOOTROM_OFFSET, 16K)
TIMESTAMP(BOOTROM_OFFSET + 0x4000, 4K)
PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 8K)
PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
-
BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
+ VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)
+ VERSTAGE(BOOTROM_OFFSET + 0x33000, 52K)
ROMSTAGE(BOOTROM_OFFSET + 0x40000, 256K)
+
SRAM_END(BOOTROM_OFFSET + 0x80000)
+
TTB(BOOTROM_OFFSET + 0x80000, 512K)
RAMSTAGE(BOOTROM_OFFSET + 0x100000, 512K)
/* Stack for secondary CPUs */