diff options
Diffstat (limited to 'src/soc/broadcom')
3 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h index 007a80aa48..bce52226ac 100755 --- a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h +++ b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h @@ -154,6 +154,6 @@ enum drc_reg_set { #define DRC_REG_WRITE(unit, channel, reg, rv) \ soc_reg32_set((volatile uint32*)(channel + 4 * reg), rv) -#endif /* #ifndef __SOC_BROADCOM_CYGNUS_DDR_BIST_H__*/ +#endif /* __SOC_BROADCOM_CYGNUS_DDR_BIST_H__ */ /* End of File */ diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h index e9eec9ab4c..166cc0bb86 100755 --- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h +++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h @@ -11266,6 +11266,6 @@ #define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_SHIFT 0 #define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000 -#endif /* #ifndef __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__ */ +#endif /* __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__ */ /* End of File */ diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h index 0efd3ac5e9..97fba1740c 100755 --- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h +++ b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h @@ -1145,6 +1145,6 @@ extern int soc_ydc_ddr_bist_run(int unit, int phy_ndx, /**************************************************************************** * Datatype Definitions. ***************************************************************************/ -#endif /* #ifndef __SOC_BROADCOM_CYGNUS_YDC_DDR_BIST_H__ */ +#endif /* __SOC_BROADCOM_CYGNUS_YDC_DDR_BIST_H__ */ /* End of File */ |