5 files changed, 6 insertions, 80 deletions

diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 11410ae91f..9738d19149 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -38,6 +38,7 @@ config SOC_AMD_PICASSO
 	select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
 	select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
 	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
+	select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS
 	select SOC_AMD_COMMON_BLOCK_HAS_ESPI
 	select SOC_AMD_COMMON_BLOCK_HDA
diff --git a/src/soc/amd/picasso/acpi/northbridge.asl b/src/soc/amd/picasso/acpi/northbridge.asl
index 99d04b5ba6..688f138123 100644
--- a/src/soc/amd/picasso/acpi/northbridge.asl
+++ b/src/soc/amd/picasso/acpi/northbridge.asl
@@ -1,8 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 /* Note: Only need HID on Primary Bus */
-External (TOM1)
-External (TOM2)
 Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */
 Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
 
diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
index 1f2c0d9310..898914cddf 100644
--- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/ioapic.h>
-
 /* System Bus */
 /*  _SB.PCI0 */
 
@@ -23,74 +21,3 @@ Method(_OSC,4)
 /* 0:14.3 - LPC */
 #include <soc/amd/common/acpi/lpc.asl>
 #include <soc/amd/common/acpi/platform.asl>
-
-Name(CRES, ResourceTemplate() {
-	/* Set the Bus number and Secondary Bus number for the PCI0 device
-	 * The Secondary bus range for PCI0 lets the system
-	 * know what bus values are allowed on the downstream
-	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI buses can have 256 secondary buses which
-	 * range from [0-0xFF] but they do not need to be
-	 * sequential.
-	 */
-	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x00ff,		/* range maximum */
-		0x0000,		/* translation */
-		0x0100,		/* length */
-		,, PSB0)		/* ResourceSourceIndex, ResourceSource, DescriptorName */
-
-	IO(Decode16, 0x0cf8, 0x0cf8, 1,	8)
-
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x0cf7,		/* range maximum */
-		0x0000,		/* translation */
-		0x0cf8		/* length */
-	)
-
-	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
-		0x0000,		/* address granularity */
-		0x0d00,		/* range minimum */
-		0xffff,		/* range maximum */
-		0x0000,		/* translation */
-		0xf300		/* length */
-	)
-
-	/* VGA memory (0xa0000-0xbffff) */
-	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
-			Cacheable, ReadWrite,
-			0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
-			0x00020000)
-	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
-			Cacheable, ReadOnly,
-			0x00000000, 0x000c0000, 0x000dffff, 0x00000000,
-			0x00020000)
-
-	/* memory space for PCI BARs below 4GB */
-	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
-			NonCacheable, ReadWrite,
-			0x00000000, 0x00000000, 0x00000000, 0x00000000,
-			0x00000000,,, PM01)
-}) /* End Name(_SB.PCI0.CRES) */
-
-Method(_CRS, 0) {
-	/* Find PCI resource area in CRES */
-	CreateDwordField (CRES, ^PM01._MIN, P1MN)
-	CreateDwordField (CRES, ^PM01._MAX, P1MX)
-	CreateDwordField (CRES, ^PM01._LEN, P1LN)
-
-	/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
-	P1MN = TOM1
-	P1MX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
-	P1LN = P1MX - P1MN + 1
-
-	CreateWordField(CRES, ^PSB0._MAX, BMAX)
-	CreateWordField(CRES, ^PSB0._LEN, BLEN)
-	BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
-	BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
-
-	Return(CRES) /* note to change the Name buffer */
-} /* end of Method(_SB.PCI0._CRS) */
diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c
index 782c1c3a6e..067c4a0734 100644
--- a/src/soc/amd/picasso/chip.c
+++ b/src/soc/amd/picasso/chip.c
@@ -27,10 +27,11 @@ static const char *soc_acpi_name(const struct device *dev)
 };
 
 struct device_operations picasso_pci_domain_ops = {
-	.read_resources	  = pci_domain_read_resources,
-	.set_resources	  = pci_domain_set_resources,
-	.scan_bus	  = pci_domain_scan_bus,
-	.acpi_name	  = soc_acpi_name,
+	.read_resources	= amd_pci_domain_read_resources,
+	.set_resources	= pci_domain_set_resources,
+	.scan_bus	= amd_pci_domain_scan_bus,
+	.acpi_name	= soc_acpi_name,
+	.acpi_fill_ssdt	= amd_pci_domain_fill_ssdt,
 };
 
 static void soc_init(void *chip_info)
diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c
index 65021a3f55..7a83197f51 100644
--- a/src/soc/amd/picasso/root_complex.c
+++ b/src/soc/amd/picasso/root_complex.c
@@ -196,7 +196,6 @@ static void acipgen_dptci(void)
 
 static void root_complex_fill_ssdt(const struct device *device)
 {
-	acpi_fill_root_complex_tom(device);
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
 		acipgen_dptci();
 }