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-rw-r--r--src/soc/amd/cezanne/Kconfig1
-rw-r--r--src/soc/amd/cezanne/chip.h7
-rw-r--r--src/soc/amd/cezanne/fch.c90
-rw-r--r--src/soc/amd/common/block/include/amdblocks/pci_clk_req.h17
-rw-r--r--src/soc/amd/common/block/pci/Kconfig7
-rw-r--r--src/soc/amd/common/block/pci/Makefile.inc1
-rw-r--r--src/soc/amd/common/block/pci/pcie_clk_req.c96
7 files changed, 125 insertions, 94 deletions
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index b8209f83a9..546ea20085 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -58,6 +58,7 @@ config SOC_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_PCI
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
+ select SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
select SOC_AMD_COMMON_BLOCK_PM
select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
select SOC_AMD_COMMON_BLOCK_PSP_GEN2
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 00eb560b64..a8b7f22c7f 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -5,6 +5,7 @@
#include <amdblocks/chip.h>
#include <amdblocks/i2c.h>
+#include <amdblocks/pci_clk_req.h>
#include <gpio.h>
#include <soc/i2c.h>
#include <soc/southbridge.h>
@@ -12,12 +13,6 @@
#include <types.h>
#include <vendorcode/amd/fsp/cezanne/FspUsb.h>
-enum gpp_clk_req {
- GPP_CLK_ON, /* GPP clock always on; default */
- GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
- GPP_CLK_OFF, /* GPP clk off */
-};
-
struct soc_amd_cezanne_config {
struct soc_amd_common_config common_config;
u8 i2c_scl_reset;
diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c
index b791037e0d..7227d20be8 100644
--- a/src/soc/amd/cezanne/fch.c
+++ b/src/soc/amd/cezanne/fch.c
@@ -3,6 +3,7 @@
#include <amdblocks/acpi.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/amd_pci_util.h>
+#include <amdblocks/pci_clk_req.h>
#include <amdblocks/gpio.h>
#include <amdblocks/i2c.h>
#include <amdblocks/smi.h>
@@ -134,93 +135,6 @@ static void fch_init_resets(void)
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
}
-/* Update gpp glk req config based on DXIO descriptors and enabled devices. */
-static void gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config,
- size_t gpp_clk_config_num)
-{
- const fsp_dxio_descriptor *dxio_descs = NULL;
- const fsp_ddi_descriptor *ddi_descs = NULL;
- size_t dxio_num = 0;
- size_t ddi_num = 0;
-
- mainboard_get_dxio_ddi_descriptors(&dxio_descs, &dxio_num, &ddi_descs, &ddi_num);
- if (dxio_descs == NULL) {
- printk(BIOS_WARNING,
- "No DXIO descriptors found, GPP clk req may not reflect enabled devices\n");
- return;
- }
-
- for (int i = 0; i < dxio_num; i++) {
- const fsp_dxio_descriptor *dxio_desc = &dxio_descs[i];
-
- /* Only consider PCIe and unused engine types. */
- if (dxio_desc->engine_type != PCIE_ENGINE
- && dxio_desc->engine_type != UNUSED_ENGINE)
- continue;
- enum cpm_clk_req dxio_clk_req = dxio_desc->clk_req;
-
- /* CLK_DISABLE means there's no corresponding clk req line in use */
- if (dxio_clk_req == CLK_DISABLE)
- continue;
-
- /*
- * dxio_clk_req is only 4 bits so having CLK_ENABLE as a value for
- * a descriptor should cause a compiler error. 0xF isn't a
- * valid clk_req value according to AMD's internal code either.
- * This is here to draw attention in case this code is ever used
- * in a situation where this has changed.
- */
- if (dxio_clk_req == (CLK_ENABLE & 0xF)) {
- printk(BIOS_WARNING,
- "CLK_ENABLE is an invalid clk_req value for PCIe device %d.%d, DXIO descriptor %d\n",
- dxio_desc->device_number, dxio_desc->function_number, i);
- continue;
- }
-
- /* cpm_clk_req 0 is CLK_DISABLE */
- int gpp_req_index = dxio_clk_req - CLK_REQ0;
- /* Ensure that our index is valid */
- if (gpp_req_index < 0 || gpp_req_index >= gpp_clk_config_num) {
- printk(BIOS_ERR, "Failed to convert DXIO clk req value %d to GPP clk req index for PCIe device %d.%d, DXIO descriptor %d, clk req settings may be incorrect\n",
- dxio_clk_req, dxio_desc->device_number,
- dxio_desc->function_number, i);
- continue;
- }
-
- const struct device *pci_device = pcidev_path_on_root(
- PCI_DEVFN(dxio_desc->device_number, dxio_desc->function_number));
- if (pci_device == NULL) {
- gpp_clk_config[gpp_req_index] = GPP_CLK_OFF;
- printk(BIOS_WARNING,
- "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n",
- dxio_desc->device_number, dxio_desc->function_number, i,
- gpp_req_index);
- continue;
- }
-
- /* PCIe devices haven't been fully set up yet, so directly read the vendor id
- * and device id to determine if a device is physically present. If a device
- * is not present then the id should be 0xffffffff. 0x00000000, 0xffff0000,
- * and 0x0000ffff are there to account for any odd failure cases. */
- u32 id = pci_read_config32(pci_device, PCI_VENDOR_ID);
- bool enabled = pci_device->enabled && (id != 0xffffffff) &&
- (id != 0x00000000) && (id != 0x0000ffff) && (id != 0xffff0000);
-
- /* Inform of possible mismatches between devices and SoC gpp_clk_config. */
- if (!enabled && gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) {
- gpp_clk_config[gpp_req_index] = GPP_CLK_OFF;
- printk(BIOS_INFO,
- "PCIe device %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n",
- dxio_desc->device_number, dxio_desc->function_number,
- gpp_req_index, i);
- } else if (enabled && gpp_clk_config[gpp_req_index] == GPP_CLK_OFF) {
- printk(BIOS_INFO,
- "PCIe device %d.%d enabled, GPP clk req is off, DXIO descriptor %d\n",
- dxio_desc->device_number, dxio_desc->function_number, i);
- }
- }
-}
-
/* Configure the general purpose PCIe clock outputs according to the devicetree settings */
static void gpp_clk_setup(void)
{
@@ -239,7 +153,7 @@ static void gpp_clk_setup(void)
uint32_t gpp_clk_ctl = misc_read32(GPP_CLK_CNTRL);
- gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT);
+ pcie_gpp_dxio_update_clk_req_config(&cfg->gpp_clk_config[0], GPP_CLK_OUTPUT_COUNT);
for (int i = 0; i < GPP_CLK_OUTPUT_COUNT; i++) {
gpp_clk_ctl &= ~GPP_CLK_REQ_MASK(gpp_clk_shift_lut[i]);
diff --git a/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
new file mode 100644
index 0000000000..32dadf45b2
--- /dev/null
+++ b/src/soc/amd/common/block/include/amdblocks/pci_clk_req.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_BLOCK_PCI_GPP_H
+#define AMD_BLOCK_PCI_GPP_H
+
+#include <soc/platform_descriptors.h>
+
+enum gpp_clk_req {
+ GPP_CLK_ON, /* GPP clock always on; default */
+ GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
+ GPP_CLK_OFF, /* GPP clk off */
+};
+
+void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config,
+ size_t gpp_clk_config_num);
+
+#endif
diff --git a/src/soc/amd/common/block/pci/Kconfig b/src/soc/amd/common/block/pci/Kconfig
index 302a6b8497..1c21833bd2 100644
--- a/src/soc/amd/common/block/pci/Kconfig
+++ b/src/soc/amd/common/block/pci/Kconfig
@@ -16,3 +16,10 @@ config SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
depends on SOC_AMD_COMMON_BLOCK_PCI
help
Select this option to use AMD common PCIe GPP driver.
+
+config SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ
+ bool
+ depends on SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
+ help
+ This option includes code to disable PCIe clock request if the corresponding
+ PCIe device is disabled.
diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc
index e013777acc..03958c7543 100644
--- a/src/soc/amd/common/block/pci/Makefile.inc
+++ b/src/soc/amd/common/block/pci/Makefile.inc
@@ -4,6 +4,7 @@ ramstage-y += amd_pci_util.c
ramstage-y += pci_routing_info.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_prt.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER) += pcie_gpp.c
+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCIE_CLK_REQ) += pcie_clk_req.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_PCI
diff --git a/src/soc/amd/common/block/pci/pcie_clk_req.c b/src/soc/amd/common/block/pci/pcie_clk_req.c
new file mode 100644
index 0000000000..881c650ed4
--- /dev/null
+++ b/src/soc/amd/common/block/pci/pcie_clk_req.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <amdblocks/pci_clk_req.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/platform_descriptors.h>
+
+/* Update gpp glk req config based on DXIO descriptors and enabled devices. */
+void pcie_gpp_dxio_update_clk_req_config(enum gpp_clk_req *gpp_clk_config,
+ size_t gpp_clk_config_num)
+{
+ const fsp_dxio_descriptor *dxio_descs = NULL;
+ const fsp_ddi_descriptor *ddi_descs = NULL;
+ size_t dxio_num = 0;
+ size_t ddi_num = 0;
+
+ mainboard_get_dxio_ddi_descriptors(&dxio_descs, &dxio_num, &ddi_descs, &ddi_num);
+ if (dxio_descs == NULL) {
+ printk(BIOS_WARNING,
+ "No DXIO descriptors found, GPP clk req may not reflect enabled devices\n");
+ return;
+ }
+
+ for (int i = 0; i < dxio_num; i++) {
+ const fsp_dxio_descriptor *dxio_desc = &dxio_descs[i];
+
+ /* Only consider PCIe and unused engine types. */
+ if (dxio_desc->engine_type != PCIE_ENGINE
+ && dxio_desc->engine_type != UNUSED_ENGINE)
+ continue;
+ enum cpm_clk_req dxio_clk_req = dxio_desc->clk_req;
+
+ /* CLK_DISABLE means there's no corresponding clk req line in use */
+ if (dxio_clk_req == CLK_DISABLE)
+ continue;
+
+ /*
+ * dxio_clk_req is only 4 bits so having CLK_ENABLE as a value for
+ * a descriptor should cause a compiler error. 0xF isn't a
+ * valid clk_req value according to AMD's internal code either.
+ * This is here to draw attention in case this code is ever used
+ * in a situation where this has changed.
+ */
+ if (dxio_clk_req == (CLK_ENABLE & 0xF)) {
+ printk(BIOS_WARNING,
+ "CLK_ENABLE is an invalid clk_req value for PCIe device %d.%d, DXIO descriptor %d\n",
+ dxio_desc->device_number, dxio_desc->function_number, i);
+ continue;
+ }
+
+ /* cpm_clk_req 0 is CLK_DISABLE */
+ int gpp_req_index = dxio_clk_req - CLK_REQ0;
+ /* Ensure that our index is valid */
+ if (gpp_req_index < 0 || gpp_req_index >= gpp_clk_config_num) {
+ printk(BIOS_ERR,
+ "Failed to convert DXIO clk req value %d to GPP clk req index for PCIe device %d.%d, DXIO descriptor %d, clk req settings may be incorrect\n",
+ dxio_clk_req, dxio_desc->device_number,
+ dxio_desc->function_number, i);
+ continue;
+ }
+
+ const struct device *pci_device = pcidev_path_on_root(
+ PCI_DEVFN(dxio_desc->device_number, dxio_desc->function_number));
+ if (pci_device == NULL) {
+ gpp_clk_config[gpp_req_index] = GPP_CLK_OFF;
+ printk(BIOS_WARNING,
+ "Cannot find PCIe device %d.%d, disabling GPP clk req %d, DXIO descriptor %d\n",
+ dxio_desc->device_number, dxio_desc->function_number, i,
+ gpp_req_index);
+ continue;
+ }
+
+ /* PCIe devices haven't been fully set up yet, so directly read the vendor id
+ * and device id to determine if a device is physically present. If a device
+ * is not present then the id should be 0xffffffff. 0x00000000, 0xffff0000,
+ * and 0x0000ffff are there to account for any odd failure cases. */
+ u32 id = pci_read_config32(pci_device, PCI_VENDOR_ID);
+ bool enabled = pci_device->enabled && (id != 0xffffffff) && (id != 0x00000000)
+ && (id != 0x0000ffff) && (id != 0xffff0000);
+
+ /* Inform of possible mismatches between devices and SoC gpp_clk_config. */
+ if (!enabled && gpp_clk_config[gpp_req_index] != GPP_CLK_OFF) {
+ gpp_clk_config[gpp_req_index] = GPP_CLK_OFF;
+ printk(BIOS_INFO,
+ "PCIe device %d.%d disabled, disabling GPP clk req %d, DXIO descriptor %d\n",
+ dxio_desc->device_number, dxio_desc->function_number,
+ gpp_req_index, i);
+ } else if (enabled && gpp_clk_config[gpp_req_index] == GPP_CLK_OFF) {
+ printk(BIOS_INFO,
+ "PCIe device %d.%d enabled, GPP clk req is off, DXIO descriptor %d\n",
+ dxio_desc->device_number, dxio_desc->function_number, i);
+ }
+ }
+}