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-rw-r--r--src/soc/amd/cezanne/romstage.c2
-rw-r--r--src/soc/amd/common/block/cpu/car/cache_as_ram.S4
-rw-r--r--src/soc/amd/common/block/cpu/noncar/pre_c.S6
-rw-r--r--src/soc/amd/common/block/include/amdblocks/post_codes.h34
-rw-r--r--src/soc/amd/common/psp_verstage/include/psp_post_code.h50
-rw-r--r--src/soc/amd/glinda/romstage.c2
-rw-r--r--src/soc/amd/mendocino/romstage.c2
-rw-r--r--src/soc/amd/phoenix/romstage.c2
-rw-r--r--src/soc/amd/picasso/romstage.c2
-rw-r--r--src/soc/amd/stoneyridge/bootblock.c2
-rw-r--r--src/soc/amd/stoneyridge/chip.c6
-rw-r--r--src/soc/amd/stoneyridge/romstage.c18
12 files changed, 65 insertions, 65 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 2bf5e230c9..63a6b07dc6 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -13,7 +13,7 @@
void __noreturn romstage_main(void)
{
- post_code(POST_ROMSTAGE_MAIN);
+ post_code(POSTCODE_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
index 372f51517b..2bd3f5061e 100644
--- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S
@@ -28,7 +28,7 @@ _cache_as_ram_setup:
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
- post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
+ post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
AMD_ENABLE_STACK
@@ -42,7 +42,7 @@ bootblock_pre_c_entry:
pushl %eax /* tsc[31:0] */
before_carstage:
- post_code(POST_BOOTBLOCK_PRE_C_DONE)
+ post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE)
call bootblock_c_entry
/* Never reached */
diff --git a/src/soc/amd/common/block/cpu/noncar/pre_c.S b/src/soc/amd/common/block/cpu/noncar/pre_c.S
index 72d778886a..eb556fabd0 100644
--- a/src/soc/amd/common/block/cpu/noncar/pre_c.S
+++ b/src/soc/amd/common/block/cpu/noncar/pre_c.S
@@ -7,7 +7,7 @@
.global bootblock_resume_entry
bootblock_resume_entry:
- post_code(POST_BOOTBLOCK_RESUME_ENTRY)
+ post_code(POSTCODE_BOOTBLOCK_RESUME_ENTRY)
/* Get an early timestamp */
rdtsc
@@ -24,7 +24,7 @@ bootblock_resume_entry:
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
- post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
+ post_code(POSTCODE_BOOTBLOCK_PRE_C_ENTRY)
#if ENV_X86_64
#include <cpu/x86/64bit/entry64.inc>
@@ -57,7 +57,7 @@ bootblock_pre_c_entry:
pushl %eax /* tsc[31:0] */
#endif
- post_code(POST_BOOTBLOCK_PRE_C_DONE)
+ post_code(POSTCODE_BOOTBLOCK_PRE_C_DONE)
call bootblock_c_entry
/* Never reached */
diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h
index 5251769731..10056e7b0a 100644
--- a/src/soc/amd/common/block/include/amdblocks/post_codes.h
+++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h
@@ -3,31 +3,31 @@
#ifndef AMD_BLOCK_POST_CODES_H
#define AMD_BLOCK_POST_CODES_H
-#define POST_AGESA_AMDINITRESET 0x37
-#define POST_AGESA_AMDINITEARLY 0x38
+#define POSTCODE_AGESA_AMDINITRESET 0x37
+#define POSTCODE_AGESA_AMDINITEARLY 0x38
-#define POST_ROMSTAGE_MAIN 0x40
+#define POSTCODE_ROMSTAGE_MAIN 0x40
-#define POST_AGESA_AMDINITPOST 0x40
-#define POST_AGESA_AMDINITPOST_DONE 0x41
+#define POSTCODE_AGESA_AMDINITPOST 0x40
+#define POSTCODE_AGESA_AMDINITPOST_DONE 0x41
-#define POST_PSP_NOTIFY_DRAM 0x42
-#define POST_PSP_NOTIFY_DRAM_DONE 0x43
+#define POSTCODE_PSP_NOTIFY_DRAM 0x42
+#define POSTCODE_PSP_NOTIFY_DRAM_DONE 0x43
-#define POST_ROMSTAGE_RUN_POSTCAR 0x44
+#define POSTCODE_ROMSTAGE_RUN_POSTCAR 0x44
-#define POST_PSP_LOAD_SMU 0x46
-#define POST_AGESA_AMDINITENV 0x47
-#define POST_AGESA_AMDS3LATERESTORE 0x48
+#define POSTCODE_PSP_LOAD_SMU 0x46
+#define POSTCODE_AGESA_AMDINITENV 0x47
+#define POSTCODE_AGESA_AMDS3LATERESTORE 0x48
-#define POST_AGESA_AMDINITRESUME 0x60
-#define POST_AGESA_AMDINITRESUME_DONE 0x61
+#define POSTCODE_AGESA_AMDINITRESUME 0x60
+#define POSTCODE_AGESA_AMDINITRESUME_DONE 0x61
-#define POST_BOOTBLOCK_SOC_EARLY_INIT 0x90
+#define POSTCODE_BOOTBLOCK_SOC_EARLY_INIT 0x90
-#define POST_BOOTBLOCK_RESUME_ENTRY 0xb0
-#define POST_BOOTBLOCK_PRE_C_ENTRY 0xa0
-#define POST_BOOTBLOCK_PRE_C_DONE 0xa2
+#define POSTCODE_BOOTBLOCK_RESUME_ENTRY 0xb0
+#define POSTCODE_BOOTBLOCK_PRE_C_ENTRY 0xa0
+#define POSTCODE_BOOTBLOCK_PRE_C_DONE 0xa2
#endif
diff --git a/src/soc/amd/common/psp_verstage/include/psp_post_code.h b/src/soc/amd/common/psp_verstage/include/psp_post_code.h
index 44464b6aa0..56b2a80c40 100644
--- a/src/soc/amd/common/psp_verstage/include/psp_post_code.h
+++ b/src/soc/amd/common/psp_verstage/include/psp_post_code.h
@@ -3,33 +3,33 @@
#ifndef PSP_POST_CODE_H
#define PSP_POST_CODE_H
-#define POSTCODE_ENTERED_PSP_VERSTAGE 0x00
-#define POSTCODE_CONSOLE_INIT 0x01
-#define POSTCODE_EARLY_INIT 0x02
-#define POSTCODE_LATE_INIT 0x03
-#define POSTCODE_VERSTAGE_MAIN 0x04
-#define POSTCODE_VERSTAGE_S0I3_RESUME 0x05
+#define POSTCODE_ENTERED_PSP_VERSTAGE 0x00
+#define POSTCODE_CONSOLE_INIT 0x01
+#define POSTCODE_EARLY_INIT 0x02
+#define POSTCODE_LATE_INIT 0x03
+#define POSTCODE_VERSTAGE_MAIN 0x04
+#define POSTCODE_VERSTAGE_S0I3_RESUME 0x05
-#define POSTCODE_SAVE_BUFFERS 0x0E
-#define POSTCODE_UPDATE_BOOT_REGION 0x0F
+#define POSTCODE_SAVE_BUFFERS 0x0E
+#define POSTCODE_UPDATE_BOOT_REGION 0x0F
-#define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0
-#define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1
-#define POSTCODE_WORKBUF_SAVE_ERROR 0xC2
-#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3
-#define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4
-#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5
-#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR 0xC6
-#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7
-#define POSTCODE_FMAP_REGION_MISSING 0xC8
-#define POSTCODE_AMD_FW_MISSING 0xC9
-#define POSTCODE_CMOS_RECOVERY 0xCA
-#define POSTCODE_EARLY_INIT_ERROR 0xCB
-#define POSTCODE_INIT_TPM_FAILED 0xCC
-#define POSTCODE_MAP_SPI_ROM_FAILED 0xCD
+#define POSTCODE_DEFAULT_BUFFER_SIZE_NOTICE 0xC0
+#define POSTCODE_WORKBUF_RESIZE_WARNING 0xC1
+#define POSTCODE_WORKBUF_SAVE_ERROR 0xC2
+#define POSTCODE_WORKBUF_BUFFER_SIZE_ERROR 0xC3
+#define POSTCODE_ROMSIG_MISMATCH_ERROR 0xC4
+#define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5
+#define POSTCODE_BHD_COOKIE_MISMATCH_ERROR 0xC6
+#define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7
+#define POSTCODE_FMAP_REGION_MISSING 0xC8
+#define POSTCODE_AMD_FW_MISSING 0xC9
+#define POSTCODE_CMOS_RECOVERY 0xCA
+#define POSTCODE_EARLY_INIT_ERROR 0xCB
+#define POSTCODE_INIT_TPM_FAILED 0xCC
+#define POSTCODE_MAP_SPI_ROM_FAILED 0xCD
-#define POSTCODE_UNMAP_SPI_ROM 0xF0
-#define POSTCODE_UNMAP_FCH_DEVICES 0xF1
-#define POSTCODE_LEAVING_VERSTAGE 0xF2
+#define POSTCODE_UNMAP_SPI_ROM 0xF0
+#define POSTCODE_UNMAP_FCH_DEVICES 0xF1
+#define POSTCODE_LEAVING_VERSTAGE 0xF2
#endif
diff --git a/src/soc/amd/glinda/romstage.c b/src/soc/amd/glinda/romstage.c
index 2bf5e230c9..63a6b07dc6 100644
--- a/src/soc/amd/glinda/romstage.c
+++ b/src/soc/amd/glinda/romstage.c
@@ -13,7 +13,7 @@
void __noreturn romstage_main(void)
{
- post_code(POST_ROMSTAGE_MAIN);
+ post_code(POSTCODE_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
diff --git a/src/soc/amd/mendocino/romstage.c b/src/soc/amd/mendocino/romstage.c
index 046c351f77..83a8bf9750 100644
--- a/src/soc/amd/mendocino/romstage.c
+++ b/src/soc/amd/mendocino/romstage.c
@@ -14,7 +14,7 @@
void __noreturn romstage_main(void)
{
- post_code(POST_ROMSTAGE_MAIN);
+ post_code(POSTCODE_ROMSTAGE_MAIN);
if (CONFIG(WRITE_STB_BUFFER_TO_CONSOLE))
write_stb_to_console();
diff --git a/src/soc/amd/phoenix/romstage.c b/src/soc/amd/phoenix/romstage.c
index 2bf5e230c9..63a6b07dc6 100644
--- a/src/soc/amd/phoenix/romstage.c
+++ b/src/soc/amd/phoenix/romstage.c
@@ -13,7 +13,7 @@
void __noreturn romstage_main(void)
{
- post_code(POST_ROMSTAGE_MAIN);
+ post_code(POSTCODE_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call */
fill_chipset_state();
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index 846460df3b..c43b249487 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -14,7 +14,7 @@
void __noreturn romstage_main(void)
{
- post_code(POST_ROMSTAGE_MAIN);
+ post_code(POSTCODE_ROMSTAGE_MAIN);
/* Snapshot chipset state prior to any FSP call. */
fill_chipset_state();
diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c
index 1d41477e4d..a1ddb5ce6d 100644
--- a/src/soc/amd/stoneyridge/bootblock.c
+++ b/src/soc/amd/stoneyridge/bootblock.c
@@ -77,7 +77,7 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
void bootblock_soc_early_init(void)
{
bootblock_fch_early_init();
- post_code(POST_BOOTBLOCK_SOC_EARLY_INIT);
+ post_code(POSTCODE_BOOTBLOCK_SOC_EARLY_INIT);
}
void bootblock_soc_init(void)
diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c
index 60bc921d93..eaa0e9ad6c 100644
--- a/src/soc/amd/stoneyridge/chip.c
+++ b/src/soc/amd/stoneyridge/chip.c
@@ -108,15 +108,15 @@ struct chip_operations soc_amd_stoneyridge_ops = {
static void earliest_ramstage(void *unused)
{
if (!acpi_is_wakeup_s3()) {
- post_code(POST_PSP_LOAD_SMU);
+ post_code(POSTCODE_PSP_LOAD_SMU);
if (CONFIG(SOC_AMD_PSP_SELECTABLE_SMU_FW))
psp_load_named_blob(BLOB_SMU_FW2, "smu_fw2");
- post_code(POST_AGESA_AMDINITENV);
+ post_code(POSTCODE_AGESA_AMDINITENV);
do_agesawrapper(AMD_INIT_ENV, "amdinitenv");
} else {
/* Complete the initial system restoration */
- post_code(POST_AGESA_AMDS3LATERESTORE);
+ post_code(POSTCODE_AGESA_AMDS3LATERESTORE);
do_agesawrapper(AMD_S3LATE_RESTORE, "amds3laterestore");
}
}
diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c
index 460218e73c..fc918f916f 100644
--- a/src/soc/amd/stoneyridge/romstage.c
+++ b/src/soc/amd/stoneyridge/romstage.c
@@ -37,10 +37,10 @@ void __weak mainboard_romstage_entry(void)
static void agesa_call(void)
{
- post_code(POST_AGESA_AMDINITRESET);
+ post_code(POSTCODE_AGESA_AMDINITRESET);
do_agesawrapper(AMD_INIT_RESET, "amdinitreset");
- post_code(POST_AGESA_AMDINITEARLY);
+ post_code(POSTCODE_AGESA_AMDINITEARLY);
/* APs will not exit amdinitearly */
do_agesawrapper(AMD_INIT_EARLY, "amdinitearly");
}
@@ -68,10 +68,10 @@ void __noreturn romstage_main(void)
bsp_agesa_call();
if (!s3_resume) {
- post_code(POST_AGESA_AMDINITPOST);
+ post_code(POSTCODE_AGESA_AMDINITPOST);
do_agesawrapper(AMD_INIT_POST, "amdinitpost");
- post_code(POST_AGESA_AMDINITPOST_DONE);
+ post_code(POSTCODE_AGESA_AMDINITPOST_DONE);
/*
* TODO: This is a hack to work around current AGESA behavior.
* AGESA needs to change to reflect that coreboot owns
@@ -101,16 +101,16 @@ void __noreturn romstage_main(void)
wrmsr(SYSCFG_MSR, sys_cfg);
} else {
printk(BIOS_INFO, "S3 detected\n");
- post_code(POST_AGESA_AMDINITRESUME);
+ post_code(POSTCODE_AGESA_AMDINITRESUME);
do_agesawrapper(AMD_INIT_RESUME, "amdinitresume");
- post_code(POST_AGESA_AMDINITRESUME_DONE);
+ post_code(POSTCODE_AGESA_AMDINITRESUME_DONE);
}
- post_code(POST_PSP_NOTIFY_DRAM);
+ post_code(POSTCODE_PSP_NOTIFY_DRAM);
psp_notify_dram();
- post_code(POST_PSP_NOTIFY_DRAM_DONE);
+ post_code(POSTCODE_PSP_NOTIFY_DRAM_DONE);
if (cbmem_recovery(s3_resume))
printk(BIOS_CRIT, "Failed to recover cbmem\n");
if (romstage_handoff_init(s3_resume))
@@ -119,7 +119,7 @@ void __noreturn romstage_main(void)
if (CONFIG(SMM_TSEG))
smm_list_regions();
- post_code(POST_ROMSTAGE_RUN_POSTCAR);
+ post_code(POSTCODE_ROMSTAGE_RUN_POSTCAR);
prepare_and_run_postcar();
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-28 05:59:21 +0000