summaryrefslogtreecommitdiff
path: root/src/soc/amd
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/chip.c3
-rw-r--r--src/soc/amd/cezanne/romstage.c3
2 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/chip.c b/src/soc/amd/cezanne/chip.c
index fd930896a7..4a39024b1b 100644
--- a/src/soc/amd/cezanne/chip.c
+++ b/src/soc/amd/cezanne/chip.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h>
#include <device/device.h>
#include <fsp/api.h>
#include <soc/southbridge.h>
@@ -12,7 +13,7 @@ static void enable_dev(struct device *dev)
static void soc_init(void *chip_info)
{
- fsp_silicon_init(false); /* no S3 support yet */
+ fsp_silicon_init(acpi_is_wakeup_s3());
fch_init(chip_info);
}
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index 509addfa52..f790def747 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h>
#include <arch/cpu.h>
#include <console/console.h>
#include <fsp/api.h>
@@ -19,7 +20,7 @@ asmlinkage void car_stage_entry(void)
u32 val = cpuid_eax(1);
printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
- fsp_memory_init(false); /* no S3 resume yet */
+ fsp_memory_init(acpi_is_wakeup_s3());
run_ramstage();
}