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-rw-r--r--src/soc/amd/picasso/chip.h4
-rw-r--r--src/soc/amd/picasso/romstage.c4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 8d4e0d3875..80cb1ceab2 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -72,6 +72,10 @@ struct soc_amd_picasso_config {
uint8_t core_dldo_bypass;
uint8_t min_soc_vid_offset;
uint8_t aclk_dpm0_freq_400MHz;
+ uint32_t telemetry_vddcr_vdd_slope;
+ uint32_t telemetry_vddcr_vdd_offset;
+ uint32_t telemetry_vddcr_soc_slope;
+ uint32_t telemetry_vddcr_soc_offset;
enum {
SD_EMMC_DISABLE,
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index f038456b29..e6bc5c9c8f 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -74,6 +74,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->core_dldo_bypass = config->core_dldo_bypass;
mcfg->min_soc_vid_offset = config->min_soc_vid_offset;
mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz;
+ mcfg->telemetry_vddcr_vdd_slope = config->telemetry_vddcr_vdd_slope;
+ mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset;
+ mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope;
+ mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
}
asmlinkage void car_stage_entry(void)