diff options
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/picasso/chip.h | 31 | ||||
| -rw-r--r-- | src/soc/amd/picasso/fsp_params.c | 18 |
2 files changed, 49 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 9a7d2a5bfc..313b6c3abf 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -66,6 +66,13 @@ struct usb_pd_control { }; #define USB_PORT_COUNT 6 + +struct __packed usb3_phy_tune { + uint8_t rx_eq_delta_iq_ovrd_val; + uint8_t rx_eq_delta_iq_ovrd_en; +}; +/* the RV2 USB3 port count */ +#define RV2_USB3_PORT_COUNT 4 #define USB_PD_PORT_COUNT 2 enum sd_emmc_driver_strength { @@ -247,6 +254,30 @@ struct soc_amd_picasso_config { USB_OC_NONE = 0xf, } usb_port_overcurrent_pin[USB_PORT_COUNT]; + /* RV2 SOC Usb 3.1 PHY Parameters */ + uint8_t usb3_phy_override; + /* + * 1,RX_EQ_DELTA_IQ_OVRD_VAL- Override value for rx_eq_delta_iq. Range 0-0xF + * 2,RX_EQ_DELTA_IQ_OVRD_EN - Enable override value for rx_eq_delta_iq. Range 0-0x1 + */ + struct usb3_phy_tune usb3_phy_tune_params[RV2_USB3_PORT_COUNT]; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F */ + uint8_t usb3_rx_vref_ctrl; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1 */ + uint8_t usb3_rx_vref_ctrl_en; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1 */ + uint8_t usb_3_tx_vboost_lvl_en; + /* Override value for rx_vref_ctrl. Range 0 - 0x1F.*/ + uint8_t usb_3_rx_vref_ctrl_x; + /* Enable override value for rx_vref_ctrl. Range 0 - 0x1. */ + uint8_t usb_3_rx_vref_ctrl_en_x; + /* Override value for tx_vboost_lvl: 0 - 0x7. */ + uint8_t usb_3_tx_vboost_lvl_x; + /* Enable override value for tx_vboost_lvl. Range: 0 - 0x1. */ + uint8_t usb_3_tx_vboost_lvl_en_x; + /* The array index is the general purpose PCIe clock output number. */ enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */ diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c index df5e1e61b4..e77cbde419 100644 --- a/src/soc/amd/picasso/fsp_params.c +++ b/src/soc/amd/picasso/fsp_params.c @@ -5,6 +5,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/platform_descriptors.h> +#include <soc/soc_util.h> #include <fsp/api.h> #include "chip.h" @@ -126,6 +127,23 @@ static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg, scfg->xhci_oc_pin_select |= (cfg->usb_port_overcurrent_pin[i] & 0xf) << (i * 4); } + + if ((get_silicon_type() == SILICON_RV2) && cfg->usb3_phy_override) { + scfg->usb_3_phy_enable = cfg->usb3_phy_override; + for (i = 0; i < FSPS_UPD_RV2_USB3_PORT_COUNT; i++) { + memcpy(scfg->usb_3_port_phy_tune[i], + &cfg->usb3_phy_tune_params[i], + sizeof(scfg->usb_3_port_phy_tune[0])); + } + scfg->usb_3_rx_vref_ctrl = cfg->usb3_rx_vref_ctrl; + scfg->usb_3_rx_vref_ctrl_en = cfg->usb3_rx_vref_ctrl_en; + scfg->usb_3_tx_vboost_lvl = cfg->usb_3_tx_vboost_lvl; + scfg->usb_3_tx_vboost_lvl_en = cfg->usb_3_tx_vboost_lvl_en; + scfg->usb_3_rx_vref_ctrl_x = cfg->usb_3_rx_vref_ctrl_x; + scfg->usb_3_rx_vref_ctrl_en_x = cfg->usb_3_rx_vref_ctrl_en_x; + scfg->usb_3_tx_vboost_lvl_x = cfg->usb_3_tx_vboost_lvl_x; + scfg->usb_3_tx_vboost_lvl_en_x = cfg->usb_3_tx_vboost_lvl_en_x; + } } static void fsp_assign_ioapic_upds(FSP_S_CONFIG *scfg) |