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-rw-r--r--src/soc/amd/picasso/include/soc/nvs.h8
-rw-r--r--src/soc/amd/stoneyridge/include/soc/nvs.h8
2 files changed, 0 insertions, 16 deletions
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
index d5624d4d75..f10fbdde58 100644
--- a/src/soc/amd/picasso/include/soc/nvs.h
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -9,9 +9,7 @@
#ifndef AMD_PICASSO_NVS_H
#define AMD_PICASSO_NVS_H
-#include <commonlib/helpers.h>
#include <stdint.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/southbridge.h>
struct __packed global_nvs {
@@ -25,12 +23,6 @@ struct __packed global_nvs {
uint8_t tmps; /* 0x17 - Temperature Sensor ID */
uint8_t tcrt; /* 0x18 - Critical Threshold */
uint8_t tpsv; /* 0x19 - Passive Threshold */
- uint8_t unused[230];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif /* AMD_PICASSO_NVS_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index 9c479c6e62..e4a158c7cb 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -9,9 +9,7 @@
#ifndef __SOC_STONEYRIDGE_NVS_H__
#define __SOC_STONEYRIDGE_NVS_H__
-#include <commonlib/helpers.h>
#include <stdint.h>
-#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/southbridge.h>
struct __packed global_nvs {
@@ -32,12 +30,6 @@ struct __packed global_nvs {
uint32_t fw01; /* 0x28 - XhciFwRamAddr_Rom, Boot RAM sz/base */
uint32_t fw03; /* 0x2c - XhciFwRomAddr_Ram, Instr RAM sz/base */
uint32_t eh10; /* 0x30 - EHCI BAR */
- uint8_t unused[204];
-
- /* ChromeOS specific (0x100 - 0xfff) */
- chromeos_acpi_t chromeos;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif /* __SOC_STONEYRIDGE_NVS_H__ */