diff options
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/common/block/include/amdblocks/spi.h | 16 | ||||
| -rw-r--r-- | src/soc/amd/common/block/spi/fch_spi.c | 40 |
2 files changed, 56 insertions, 0 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index a551151d46..c4ad44f8a4 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -32,6 +32,12 @@ enum spi_read_mode { #define SPI100_ENABLE 0x20 #define SPI_USE_SPI100 BIT(0) +#define DECODE_SPI_MODE_BITS(x) ((x) & SPI_READ_MODE_MASK) +#define DECODE_SPI_MODE_UPPER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 28) & 0x06) +#define DECODE_SPI_MODE_LOWER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 18) & 0x01) +#define DECODE_SPI_READ_MODE(x) (DECODE_SPI_MODE_UPPER_BITS(x) | \ + DECODE_SPI_MODE_LOWER_BITS(x)) + /* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ #define SPI100_SPEED_CONFIG 0x22 enum spi100_speed { @@ -53,6 +59,13 @@ enum spi100_speed { #define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) +#define DECODE_SPEED_MASK 0x07 +#define DECODE_SPEED_MODE(x, shift) (((x) >> shift) & DECODE_SPEED_MASK) +#define DECODE_SPI_NORMAL_SPEED(x) DECODE_SPEED_MODE(x, 12) +#define DECODE_SPI_FAST_SPEED(x) DECODE_SPEED_MODE(x, 8) +#define DECODE_SPI_ALT_SPEED(x) DECODE_SPEED_MODE(x, 4) +#define DECODE_SPI_TPM_SPEED(x) DECODE_SPEED_MODE(x, 0) + #define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) @@ -91,6 +104,9 @@ void fch_spi_early_init(void); /* Set the SPI base address variable */ void spi_set_base(void *base); +/* Show the SPI settings */ +void show_spi_speeds_and_modes(void); + /* Get the SPI base address variable's value */ uintptr_t spi_get_bar(void); uint8_t spi_read8(uint8_t reg); diff --git a/src/soc/amd/common/block/spi/fch_spi.c b/src/soc/amd/common/block/spi/fch_spi.c index a8425149aa..38be7be8cf 100644 --- a/src/soc/amd/common/block/spi/fch_spi.c +++ b/src/soc/amd/common/block/spi/fch_spi.c @@ -10,6 +10,46 @@ #include <soc/lpc.h> #include <stdint.h> +static const char *spi_speed_str[8] = { + "66.66 Mhz", + "33.33 MHz", + "22.22 MHz", + "16.66 MHz", + "100 MHz", + "800 KHz", + "Invalid", + "Invalid" +}; + +static const char *read_mode_str[8] = { + "Normal Read (up to 33M)", + "Reserved", + "Dual IO (1-1-2)", + "Quad IO (1-1-4)", + "Dual IO (1-2-2)", + "Quad IO (1-4-4)", + "Normal Read (up to 66M)", + "Fast Read" +}; + +void show_spi_speeds_and_modes(void) +{ + uint16_t val16 = spi_read16(SPI100_SPEED_CONFIG); + uint32_t val32 = spi_read32(SPI_CNTRL0); + + printk(BIOS_DEBUG, "SPI normal read speed: %s\n", + spi_speed_str[DECODE_SPI_NORMAL_SPEED(val16)]); + printk(BIOS_DEBUG, "SPI fast read speed: %s\n", + spi_speed_str[DECODE_SPI_FAST_SPEED(val16)]); + printk(BIOS_DEBUG, "SPI alt read speed: %s\n", + spi_speed_str[DECODE_SPI_ALT_SPEED(val16)]); + printk(BIOS_DEBUG, "SPI TPM read speed: %s\n", + spi_speed_str[DECODE_SPI_TPM_SPEED(val16)]); + printk(BIOS_DEBUG, "SPI100: %s\n", + spi_read16(SPI100_ENABLE) & SPI_USE_SPI100 ? "Enabled" : "Disabled"); + printk(BIOS_DEBUG, "SPI Read Mode: %s\n", read_mode_str[DECODE_SPI_READ_MODE(val32)]); +} + static uint8_t lower_speed(uint8_t speed1, uint8_t speed2) { uint8_t speeds[] = {SPI_SPEED_800K, SPI_SPEED_16M, SPI_SPEED_22M, |