summaryrefslogtreecommitdiff
path: root/src/soc/amd
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/amd')
-rw-r--r--src/soc/amd/cezanne/acpi.c59
-rw-r--r--src/soc/amd/common/block/acpi/cpu_power_state.c59
-rw-r--r--src/soc/amd/common/block/include/amdblocks/cpu.h3
-rw-r--r--src/soc/amd/glinda/acpi.c59
-rw-r--r--src/soc/amd/mendocino/acpi.c59
-rw-r--r--src/soc/amd/phoenix/acpi.c59
-rw-r--r--src/soc/amd/picasso/acpi.c57
7 files changed, 70 insertions, 285 deletions
diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c
index 884552900e..51c62cbe6b 100644
--- a/src/soc/amd/cezanne/acpi.c
+++ b/src/soc/amd/cezanne/acpi.c
@@ -184,8 +184,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
-static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
- struct acpi_xpss_sw_pstate *pstate_xpss_values)
+size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
+ struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@@ -246,58 +246,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
-
-void generate_cpu_entries(const struct device *device)
-{
- int logical_cores;
- size_t cstate_count, pstate_count, cpu;
- acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
- struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
- struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
- uint32_t threads_per_core;
-
- const acpi_addr_t perf_ctrl = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_CTL_REG,
- };
- const acpi_addr_t perf_sts = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_STS_REG,
- };
-
- threads_per_core = get_threads_per_core();
- cstate_count = get_cstate_info(cstate_values);
- pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
- logical_cores = get_cpu_count();
-
- for (cpu = 0; cpu < logical_cores; cpu++) {
- acpigen_write_processor_device(cpu);
-
- acpigen_write_pct_package(&perf_ctrl, &perf_sts);
-
- acpigen_write_pss_object(pstate_values, pstate_count);
-
- acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
-
- if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
- acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
- HW_ALL);
- else
- acpigen_write_PSD_package(0, logical_cores, SW_ALL);
-
- acpigen_write_PPC(0);
-
- acpigen_write_CST_package(cstate_values, cstate_count);
-
- acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
- CSD_HW_ALL, 0);
-
- generate_cppc_entries(cpu);
-
- acpigen_write_processor_device_end();
- }
-
- acpigen_write_processor_package("PPKG", 0, logical_cores);
-}
diff --git a/src/soc/amd/common/block/acpi/cpu_power_state.c b/src/soc/amd/common/block/acpi/cpu_power_state.c
index d0e59af835..cefa0e46a5 100644
--- a/src/soc/amd/common/block/acpi/cpu_power_state.c
+++ b/src/soc/amd/common/block/acpi/cpu_power_state.c
@@ -2,6 +2,7 @@
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
+#include <amdblocks/cppc.h>
#include <amdblocks/cpu.h>
#include <console/console.h>
#include <cpu/amd/msr.h>
@@ -42,7 +43,7 @@ static void write_cstate_entry(acpi_cstate_t *entry, const acpi_cstate_t *data,
}
}
-size_t get_cstate_info(acpi_cstate_t *cstate_values)
+static size_t get_cstate_info(acpi_cstate_t *cstate_values)
{
size_t i;
size_t cstate_count;
@@ -63,3 +64,59 @@ size_t get_cstate_info(acpi_cstate_t *cstate_values)
return i;
}
+
+void generate_cpu_entries(const struct device *device)
+{
+ int logical_cores;
+ size_t cstate_count, pstate_count, cpu;
+ acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
+ struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
+ struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
+ uint32_t threads_per_core;
+
+ const acpi_addr_t perf_ctrl = {
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
+ .bit_width = 64,
+ .addrl = PS_CTL_REG,
+ };
+ const acpi_addr_t perf_sts = {
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
+ .bit_width = 64,
+ .addrl = PS_STS_REG,
+ };
+
+ threads_per_core = get_threads_per_core();
+ cstate_count = get_cstate_info(cstate_values);
+ pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
+ logical_cores = get_cpu_count();
+
+ for (cpu = 0; cpu < logical_cores; cpu++) {
+ acpigen_write_processor_device(cpu);
+
+ acpigen_write_pct_package(&perf_ctrl, &perf_sts);
+
+ acpigen_write_pss_object(pstate_values, pstate_count);
+
+ acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
+
+ if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
+ acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
+ HW_ALL);
+ else
+ acpigen_write_PSD_package(0, logical_cores, SW_ALL);
+
+ acpigen_write_PPC(0);
+
+ acpigen_write_CST_package(cstate_values, cstate_count);
+
+ acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
+ CSD_HW_ALL, 0);
+
+ if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_CPPC))
+ generate_cppc_entries(cpu);
+
+ acpigen_write_processor_device_end();
+ }
+
+ acpigen_write_processor_package("PPKG", 0, logical_cores);
+}
diff --git a/src/soc/amd/common/block/include/amdblocks/cpu.h b/src/soc/amd/common/block/include/amdblocks/cpu.h
index a380a2df93..998ed136fb 100644
--- a/src/soc/amd/common/block/include/amdblocks/cpu.h
+++ b/src/soc/amd/common/block/include/amdblocks/cpu.h
@@ -14,7 +14,8 @@ unsigned int get_threads_per_core(void);
void set_cstate_io_addr(void);
void write_resume_eip(void);
-size_t get_cstate_info(acpi_cstate_t *cstate_values);
+size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
+ struct acpi_xpss_sw_pstate *pstate_xpss_values);
const acpi_cstate_t *get_cstate_config_data(size_t *size);
#endif /* AMD_BLOCK_CPU_H */
diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c
index 20a69b437d..78e39cfe1f 100644
--- a/src/soc/amd/glinda/acpi.c
+++ b/src/soc/amd/glinda/acpi.c
@@ -187,8 +187,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
-static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
- struct acpi_xpss_sw_pstate *pstate_xpss_values)
+size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
+ struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@@ -249,58 +249,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
-
-void generate_cpu_entries(const struct device *device)
-{
- int logical_cores;
- size_t cstate_count, pstate_count, cpu;
- acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
- struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
- struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
- uint32_t threads_per_core;
-
- const acpi_addr_t perf_ctrl = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_CTL_REG,
- };
- const acpi_addr_t perf_sts = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_STS_REG,
- };
-
- threads_per_core = get_threads_per_core();
- cstate_count = get_cstate_info(cstate_values);
- pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
- logical_cores = get_cpu_count();
-
- for (cpu = 0; cpu < logical_cores; cpu++) {
- acpigen_write_processor_device(cpu);
-
- acpigen_write_pct_package(&perf_ctrl, &perf_sts);
-
- acpigen_write_pss_object(pstate_values, pstate_count);
-
- acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
-
- if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
- acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
- HW_ALL);
- else
- acpigen_write_PSD_package(0, logical_cores, SW_ALL);
-
- acpigen_write_PPC(0);
-
- acpigen_write_CST_package(cstate_values, cstate_count);
-
- acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
- CSD_HW_ALL, 0);
-
- generate_cppc_entries(cpu);
-
- acpigen_write_processor_device_end();
- }
-
- acpigen_write_processor_package("PPKG", 0, logical_cores);
-}
diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c
index 1f9e253d41..a2990abe0a 100644
--- a/src/soc/amd/mendocino/acpi.c
+++ b/src/soc/amd/mendocino/acpi.c
@@ -186,8 +186,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
-static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
- struct acpi_xpss_sw_pstate *pstate_xpss_values)
+size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
+ struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@@ -248,58 +248,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
-
-void generate_cpu_entries(const struct device *device)
-{
- int logical_cores;
- size_t cstate_count, pstate_count, cpu;
- acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
- struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
- struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
- uint32_t threads_per_core;
-
- const acpi_addr_t perf_ctrl = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_CTL_REG,
- };
- const acpi_addr_t perf_sts = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_STS_REG,
- };
-
- threads_per_core = get_threads_per_core();
- cstate_count = get_cstate_info(cstate_values);
- pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
- logical_cores = get_cpu_count();
-
- for (cpu = 0; cpu < logical_cores; cpu++) {
- acpigen_write_processor_device(cpu);
-
- acpigen_write_pct_package(&perf_ctrl, &perf_sts);
-
- acpigen_write_pss_object(pstate_values, pstate_count);
-
- acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
-
- if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
- acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
- HW_ALL);
- else
- acpigen_write_PSD_package(0, logical_cores, SW_ALL);
-
- acpigen_write_PPC(0);
-
- acpigen_write_CST_package(cstate_values, cstate_count);
-
- acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
- CSD_HW_ALL, 0);
-
- generate_cppc_entries(cpu);
-
- acpigen_write_processor_device_end();
- }
-
- acpigen_write_processor_package("PPKG", 0, logical_cores);
-}
diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c
index 2646f2f1a1..ca60e8c721 100644
--- a/src/soc/amd/phoenix/acpi.c
+++ b/src/soc/amd/phoenix/acpi.c
@@ -187,8 +187,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
-static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
- struct acpi_xpss_sw_pstate *pstate_xpss_values)
+size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
+ struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@@ -249,58 +249,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
-
-void generate_cpu_entries(const struct device *device)
-{
- int logical_cores;
- size_t cstate_count, pstate_count, cpu;
- acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
- struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
- struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
- uint32_t threads_per_core;
-
- const acpi_addr_t perf_ctrl = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_CTL_REG,
- };
- const acpi_addr_t perf_sts = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_STS_REG,
- };
-
- threads_per_core = get_threads_per_core();
- cstate_count = get_cstate_info(cstate_values);
- pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
- logical_cores = get_cpu_count();
-
- for (cpu = 0; cpu < logical_cores; cpu++) {
- acpigen_write_processor_device(cpu);
-
- acpigen_write_pct_package(&perf_ctrl, &perf_sts);
-
- acpigen_write_pss_object(pstate_values, pstate_count);
-
- acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
-
- if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
- acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
- HW_ALL);
- else
- acpigen_write_PSD_package(0, logical_cores, SW_ALL);
-
- acpigen_write_PPC(0);
-
- acpigen_write_CST_package(cstate_values, cstate_count);
-
- acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
- CSD_HW_ALL, 0);
-
- generate_cppc_entries(cpu);
-
- acpigen_write_processor_device_end();
- }
-
- acpigen_write_processor_package("PPKG", 0, logical_cores);
-}
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 0bac92f136..cce78cf942 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -188,8 +188,8 @@ static uint32_t get_pstate_core_power(msr_t pstate_def)
/*
* Populate structure describing enabled p-states and return count of enabled p-states.
*/
-static size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
- struct acpi_xpss_sw_pstate *pstate_xpss_values)
+size_t get_pstate_info(struct acpi_sw_pstate *pstate_values,
+ struct acpi_xpss_sw_pstate *pstate_xpss_values)
{
msr_t pstate_def;
size_t pstate_count, pstate;
@@ -245,56 +245,3 @@ const acpi_cstate_t *get_cstate_config_data(size_t *size)
*size = ARRAY_SIZE(cstate_cfg_table);
return cstate_cfg_table;
}
-
-void generate_cpu_entries(const struct device *device)
-{
- int logical_cores;
- size_t cstate_count, pstate_count, cpu;
- acpi_cstate_t cstate_values[MAX_CSTATE_COUNT] = { {0} };
- struct acpi_sw_pstate pstate_values[MAX_PSTATES] = { {0} };
- struct acpi_xpss_sw_pstate pstate_xpss_values[MAX_PSTATES] = { {0} };
- uint32_t threads_per_core;
-
- const acpi_addr_t perf_ctrl = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_CTL_REG,
- };
- const acpi_addr_t perf_sts = {
- .space_id = ACPI_ADDRESS_SPACE_FIXED,
- .bit_width = 64,
- .addrl = PS_STS_REG,
- };
-
- threads_per_core = get_threads_per_core();
- cstate_count = get_cstate_info(cstate_values);
- pstate_count = get_pstate_info(pstate_values, pstate_xpss_values);
- logical_cores = get_cpu_count();
-
- for (cpu = 0; cpu < logical_cores; cpu++) {
- acpigen_write_processor_device(cpu);
-
- acpigen_write_pct_package(&perf_ctrl, &perf_sts);
-
- acpigen_write_pss_object(pstate_values, pstate_count);
-
- acpigen_write_xpss_object(pstate_xpss_values, pstate_count);
-
- if (CONFIG(ACPI_SSDT_PSD_INDEPENDENT))
- acpigen_write_PSD_package(cpu / threads_per_core, threads_per_core,
- HW_ALL);
- else
- acpigen_write_PSD_package(0, logical_cores, SW_ALL);
-
- acpigen_write_PPC(0);
-
- acpigen_write_CST_package(cstate_values, cstate_count);
-
- acpigen_write_CSD_package(cpu / threads_per_core, threads_per_core,
- CSD_HW_ALL, 0);
-
- acpigen_write_processor_device_end();
- }
-
- acpigen_write_processor_package("PPKG", 0, logical_cores);
-}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 07:38:04 +0000