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-rw-r--r--src/soc/amd/mendocino/chip.h3
-rw-r--r--src/soc/amd/mendocino/fsp_m_params.c2
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h
index c206445e58..cf31cd7a30 100644
--- a/src/soc/amd/mendocino/chip.h
+++ b/src/soc/amd/mendocino/chip.h
@@ -164,6 +164,9 @@ struct soc_amd_mendocino_config {
uint8_t usb_phy_custom;
struct usb_phy_config usb_phy;
+ /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal
+ Integrity is highly recommended. */
+ uint8_t dxio_tx_vboost_enable;
};
#endif /* MENDOCINO_CHIP_H */
diff --git a/src/soc/amd/mendocino/fsp_m_params.c b/src/soc/amd/mendocino/fsp_m_params.c
index d6eae9a7be..8533743d51 100644
--- a/src/soc/amd/mendocino/fsp_m_params.c
+++ b/src/soc/amd/mendocino/fsp_m_params.c
@@ -169,6 +169,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->usb_phy_ptr = 0;
}
+ mcfg->dxio_tx_vboost_enable = config->dxio_tx_vboost_enable;
+
fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg);
mb_pre_fspm(mcfg);