diff options
Diffstat (limited to 'src/soc/amd')
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 13 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/fsp_m_params.c | 10 |
2 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index e549579644..d007a84c98 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -106,6 +106,19 @@ struct soc_amd_cezanne_config { uint8_t usb_phy_custom; struct usb_phy_config usb_phy; + + /* eDP phy tuning settings */ + uint8_t edp_phy_override; + /* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */ + uint8_t edp_physel; + + struct { + uint8_t dp_vs_pemph_level; + uint8_t tx_eq_main; + uint8_t tx_eq_pre; + uint8_t tx_eq_post; + uint8_t tx_vboost_lvl; + } edp_tuningset; }; #endif /* CEZANNE_CHIP_H */ diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c index 51e04e15cd..92debe3b08 100644 --- a/src/soc/amd/cezanne/fsp_m_params.c +++ b/src/soc/amd/cezanne/fsp_m_params.c @@ -157,6 +157,16 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mcfg->usb_phy = NULL; } + if (config->edp_phy_override) { + mcfg->edp_phy_override = config->edp_phy_override; + mcfg->edp_physel = config->edp_physel; + mcfg->dp_vs_pemph_level = config->edp_tuningset.dp_vs_pemph_level; + mcfg->tx_eq_main = config->edp_tuningset.tx_eq_main; + mcfg->tx_eq_pre = config->edp_tuningset.tx_eq_pre; + mcfg->tx_eq_post = config->edp_tuningset.tx_eq_post; + mcfg->tx_vboost_lvl = config->edp_tuningset.tx_vboost_lvl; + } + fsp_fill_pcie_ddi_descriptors(mcfg); fsp_assign_ioapic_upds(mcfg); mb_pre_fspm(); |