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-rw-r--r--src/soc/amd/stoneyridge/northbridge.c47
1 files changed, 0 insertions, 47 deletions
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 081bc1f47d..1e601cf4b7 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -3,7 +3,6 @@
#include <assert.h>
#include <amdblocks/acpi.h>
#include <amdblocks/biosram.h>
-#include <amdblocks/hda.h>
#include <device/pci_ops.h>
#include <arch/hpet.h>
#include <arch/ioapic.h>
@@ -408,49 +407,3 @@ void SetNbMidParams(GNB_MID_CONFIGURATION *params)
params->iGpuVgaMode = 0;
params->GnbIoapicAddress = IO_APIC2_ADDR;
}
-
-void hda_soc_ssdt_quirks(const struct device *dev)
-{
- const char *scope = acpi_device_path(dev);
- static const struct fieldlist list[] = {
- FIELDLIST_OFFSET(0x42),
- FIELDLIST_NAMESTR("NSDI", 1),
- FIELDLIST_NAMESTR("NSDO", 1),
- FIELDLIST_NAMESTR("NSEN", 1),
- };
- struct opregion opreg = OPREGION("AZPD", PCI_CONFIG, 0x0, 0x100);
-
- assert(scope);
-
- acpigen_write_scope(scope);
-
- /*
- * OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
- * Field (AZPD, AnyAcc, NoLock, Preserve) {
- * Offset (0x42),
- * NSDI, 1,
- * NSDO, 1,
- * NSEN, 1,
- * }
- */
- acpigen_write_opregion(&opreg);
- acpigen_write_field(opreg.name, list, ARRAY_SIZE(list),
- FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE);
-
- /*
- * Method (_INI, 0, NotSerialized) {
- * Store (Zero, NSEN)
- * Store (One, NSDO)
- * Store (One, NSDI)
- * }
- */
- acpigen_write_method("_INI", 0);
-
- acpigen_write_store_op_to_namestr(ZERO_OP, "NSEN");
- acpigen_write_store_op_to_namestr(ONE_OP, "NSDO");
- acpigen_write_store_op_to_namestr(ONE_OP, "NSDI");
-
- acpigen_pop_len(); /* Method _INI */
-
- acpigen_pop_len(); /* Scope */
-}