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-rw-r--r--src/soc/amd/stoneyridge/include/soc/northbridge.h1
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c2
2 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h
index 563dae09e1..60a6ea22bb 100644
--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h
@@ -18,6 +18,7 @@
#define __PI_STONEYRIDGE_NORTHBRIDGE_H__
#include <device/device.h>
+#include <types.h>
/* D0F0 - Root Complex */
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index bf8787c1fc..84db3dd76c 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -14,7 +14,6 @@
*/
#include <console/console.h>
-
#include <device/mmio.h>
#include <bootstate.h>
#include <cpu/x86/smm.h>
@@ -36,6 +35,7 @@
#include <soc/pci_devs.h>
#include <agesa_headers.h>
#include <soc/nvs.h>
+#include <types.h>
/*
* Table of devices that need their AOAC registers enabled and waited