diff options
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.h | 4 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/romstage.c | 14 |
2 files changed, 18 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index de6585e164..4623800848 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -24,6 +24,10 @@ struct soc_amd_stoneyridge_config { u8 spdAddrLookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; + enum { + DRAM_CONTENTS_KEEP, + DRAM_CONTENTS_CLEAR + } dram_clear_on_reset; }; typedef struct soc_amd_stoneyridge_config config_t; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index a152c1f399..9b22761f9e 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -111,3 +111,17 @@ asmlinkage void car_stage_entry(void) post_code(0x50); /* Should never see this post code. */ } + +void SetMemParams(AMD_POST_PARAMS *PostParams) +{ + const struct soc_amd_stoneyridge_config *cfg; + const struct device *dev = dev_find_slot(0, GNB_DEVFN); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "ERROR: Could not find SoC devicetree config\n"); + return; + } + + cfg = dev->chip_info; + PostParams->MemConfig.EnableMemClr = cfg->dram_clear_on_reset; +} |