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-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index ad4040759c..07c92a185c 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -254,9 +254,6 @@
#define SATA_CAPABILITIES_REG 0xfc
#define SATA_CAPABILITY_SPM BIT(12)
-/* SPI Controller (base address in D14F3xA0) */
-#define SPI_BASE_ALIGNMENT BIT(6)
-
#define SPI_CNTRL0 0x00
#define SPI_BUSY BIT(31)
#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18))