aboutsummaryrefslogtreecommitdiff
path: root/src/soc/amd/stoneyridge
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/amd/stoneyridge')
-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h24
-rw-r--r--src/soc/amd/stoneyridge/southbridge.c1
2 files changed, 2 insertions, 23 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 9450a92723..59843c1ea8 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -189,10 +189,7 @@
#define DEBUG_PORT_ENABLE BIT(18)
#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | BIT(18))
-/* FCH AOAC Registers 0xfed81e00 */
-#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2)
-#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1)
-
+/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
#define FCH_AOAC_DEV_CLK_GEN 0
#define FCH_AOAC_DEV_I2C0 5
#define FCH_AOAC_DEV_I2C1 6
@@ -204,25 +201,6 @@
#define FCH_AOAC_DEV_USB2 18
#define FCH_AOAC_DEV_USB3 23
-/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
-#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
-#define FCH_AOAC_DEVICE_STATE BIT(2)
-#define FCH_AOAC_PWR_ON_DEV BIT(3)
-#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4)
-#define FCH_AOAC_SW_REF_CLK_OK BIT(5)
-#define FCH_AOAC_SW_RST_B BIT(6)
-#define FCH_AOAC_IS_SW_CONTROL BIT(7)
-
-/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
-#define FCH_AOAC_PWR_RST_STATE BIT(0)
-#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
-#define FCH_AOAC_RST_B_STATE BIT(2)
-#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3)
-#define FCH_AOAC_D3COLD BIT(4)
-#define FCH_AOAC_CLK_OK_STATE BIT(5)
-#define FCH_AOAC_STAT0 BIT(6)
-#define FCH_AOAC_STAT1 BIT(7)
-
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
#define TOTAL_BITS(a) (8 * sizeof(a))
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 05f3072edd..b427c18635 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -12,6 +12,7 @@
#include <acpi/acpi_gnvs.h>
#include <amdblocks/amd_pci_util.h>
#include <amdblocks/agesawrapper.h>
+#include <amdblocks/aoac.h>
#include <amdblocks/reset.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/lpc.h>