diff options
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h | 20 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/southbridge.c | 59 |
2 files changed, 64 insertions, 15 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h index a8e75f6327..e160c89283 100644 --- a/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h +++ b/src/soc/amd/stoneyridge/include/soc/amd_pci_int_defs.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,9 +18,8 @@ #define __AMD_PCI_INT_DEFS_H__ /* - * PIRQ and device routing - these define the index - * into the FCH PCI_INTR 0xC00/0xC01 interrupt - * routing table + * PIRQ and device routing - these define the index into the + * FCH PCI_INTR 0xC00/0xC01 interrupt routing table. */ #define PIRQ_NC 0x1f /* Not Used */ @@ -44,26 +44,18 @@ #define PIRQ_ASF 0x12 /* ASF */ #define PIRQ_HDA 0x13 /* HDA 14h.2 */ #define PIRQ_FC 0x14 /* FC */ -#define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ #define PIRQ_SD 0x17 /* SD */ +#define PIRQ_SDIO 0x1a /* SDIO */ #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */ #define PIRQ_IMC3 0x23 /* IMC INT3 */ #define PIRQ_IMC4 0x24 /* IMC INT4 */ #define PIRQ_IMC5 0x25 /* IMC INT5 */ -#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ -#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ -#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ -#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ -#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ -#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ -#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ -#define PIRQ_IDE 0x40 /* IDE 14h.1 */ +#define PIRQ_EHCI 0x30 /* USB EHCI 12h.0 */ +#define PIRQ_XHCI 0x34 /* USB XHCI 10h.0 */ #define PIRQ_SATA 0x41 /* SATA 11h.0 */ - -#define FCH_INT_TABLE_SIZE 0x76 #define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */ #define PIRQ_I2C0 0x70 #define PIRQ_I2C1 0x71 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index dbf27bc6b8..44dbf62a1c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010-2017 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,10 +27,67 @@ #include <amd_pci_util.h> #include <soc/southbridge.h> #include <soc/smi.h> +#include <soc/amd_pci_int_defs.h> #include <fchec.h> #include <delay.h> #include <soc/pci_devs.h> +/* + * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME + * provides a visible association with the index, therefor helping + * maintainability of table. If a new index/name is defined in + * amd_pci_int_defs.h, just add the pair at the end of this table. + * Order is not important. + */ +const static struct irq_idx_name irq_association[] = { + { PIRQ_A, "INTA#\t" }, + { PIRQ_B, "INTB#\t" }, + { PIRQ_C, "INTC#\t" }, + { PIRQ_D, "INTD#\t" }, + { PIRQ_E, "INTE#\t" }, + { PIRQ_F, "INTF#\t" }, + { PIRQ_G, "INTG#\t" }, + { PIRQ_H, "INTH#\t" }, + { PIRQ_MISC, "Misc\t" }, + { PIRQ_MISC0, "Misc0\t" }, + { PIRQ_MISC1, "Misc1\t" }, + { PIRQ_MISC2, "Misc2\t" }, + { PIRQ_SIRQA, "Ser IRQ INTA" }, + { PIRQ_SIRQB, "Ser IRQ INTB" }, + { PIRQ_SIRQC, "Ser IRQ INTC" }, + { PIRQ_SIRQD, "Ser IRQ INTD" }, + { PIRQ_SCI, "SCI\t" }, + { PIRQ_SMBUS, "SMBUS\t" }, + { PIRQ_ASF, "ASF\t" }, + { PIRQ_HDA, "HDA\t" }, + { PIRQ_FC, "FC\t\t" }, + { PIRQ_PMON, "PerMon\t" }, + { PIRQ_SD, "SD\t\t" }, + { PIRQ_SDIO, "SDIO\t" }, + { PIRQ_IMC0, "IMC INT0\t" }, + { PIRQ_IMC1, "IMC INT1\t" }, + { PIRQ_IMC2, "IMC INT2\t" }, + { PIRQ_IMC3, "IMC INT3\t" }, + { PIRQ_IMC4, "IMC INT4\t" }, + { PIRQ_IMC5, "IMC INT5\t" }, + { PIRQ_EHCI, "EHCI\t" }, + { PIRQ_XHCI, "XHCI\t" }, + { PIRQ_SATA, "SATA\t" }, + { PIRQ_GPIO, "GPIO\t" }, + { PIRQ_I2C0, "I2C0\t" }, + { PIRQ_I2C1, "I2C1\t" }, + { PIRQ_I2C2, "I2C2\t" }, + { PIRQ_I2C3, "I2C3\t" }, + { PIRQ_UART0, "UART0\t" }, + { PIRQ_UART1, "UART1\t" }, +}; + +const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) +{ + *size = ARRAY_SIZE(irq_association); + return irq_association; +} + void configure_stoneyridge_uart(void) { u8 byte, byte2; |