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-rw-r--r--src/soc/amd/stoneyridge/Kconfig1
-rw-r--r--src/soc/amd/stoneyridge/smi.c5
2 files changed, 1 insertions, 5 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 47642a9fda..9bb5604391 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SMI_HANDLER
select SSE2
select RTC
+ select ACPI_NO_SMI_GNVS
config AMD_APU_STONEYRIDGE
bool
diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
index a3473aafc5..fb6d3484ad 100644
--- a/src/soc/amd/stoneyridge/smi.c
+++ b/src/soc/amd/stoneyridge/smi.c
@@ -10,11 +10,6 @@
#include <soc/southbridge.h>
#include <soc/smi.h>
-void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
-{
- printk(BIOS_DEBUG, "%s STUB!!!\n", __func__);
-}
-
/** Set the EOS bit and enable SMI generation from southbridge */
void global_smi_enable(void)
{