diff options
Diffstat (limited to 'src/soc/amd/stoneyridge/smbus.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/smbus.c | 74 |
1 files changed, 52 insertions, 22 deletions
diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index c4a022a9a9..6285d793b7 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -15,21 +15,51 @@ #include <arch/io.h> #include <stdint.h> +#include <console/console.h> #include <soc/smbus.h> #include <soc/southbridge.h> +static u8 controller_read8(u32 base, u8 reg) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + return smbus_read8(reg); + case ACPIMMIO_ASF_BASE: + return asf_read8(reg); + default: + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n", + base); + } + return 0xff; +} + +static void controller_write8(u32 base, u8 reg, u8 val) +{ + switch (base) { + case ACPIMMIO_SMBUS_BASE: + smbus_write8(reg, val); + break; + case ACPIMMIO_ASF_BASE: + asf_write8(reg, val); + break; + default: + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n", + base); + } +} + static int smbus_wait_until_ready(u32 mmio) { u32 loops; loops = SMBUS_TIMEOUT; do { u8 val; - val = smbus_read8(mmio, SMBHSTSTAT); + val = controller_read8(mmio, SMBHSTSTAT); val &= SMBHST_STAT_VAL_BITS; if (val == 0) { /* ready now */ return 0; } - smbus_write8(mmio, SMBHSTSTAT, val); + controller_write8(mmio, SMBHSTSTAT, val); } while (--loops); return -2; /* time out */ } @@ -41,12 +71,12 @@ static int smbus_wait_until_done(u32 mmio) do { u8 val; - val = smbus_read8(mmio, SMBHSTSTAT); + val = controller_read8(mmio, SMBHSTSTAT); val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ if (val & SMBHST_STAT_ERROR_BITS) return -5; /* error */ if (val == SMBHST_STAT_NOERROR) { - smbus_write8(mmio, SMBHSTSTAT, val); /* clear sts */ + controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ return 0; } } while (--loops); @@ -61,19 +91,19 @@ int do_smbus_recv_byte(u32 mmio, u8 device) return -2; /* not ready */ /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) return -3; /* timeout or error */ /* read results of transaction */ - byte = smbus_read8(mmio, SMBHSTDAT0); + byte = controller_read8(mmio, SMBHSTDAT0); return byte; } @@ -86,15 +116,15 @@ int do_smbus_send_byte(u32 mmio, u8 device, u8 val) return -2; /* not ready */ /* set the command... */ - smbus_write8(mmio, SMBHSTDAT0, val); + controller_write8(mmio, SMBHSTDAT0, val); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) @@ -111,22 +141,22 @@ int do_smbus_read_byte(u32 mmio, u8 device, u8 address) return -2; /* not ready */ /* set the command/address... */ - smbus_write8(mmio, SMBHSTCMD, address & 0xff); + controller_write8(mmio, SMBHSTCMD, address & 0xff); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) return -3; /* timeout or error */ /* read results of transaction */ - byte = smbus_read8(mmio, SMBHSTDAT0); + byte = controller_read8(mmio, SMBHSTDAT0); return byte; } @@ -139,18 +169,18 @@ int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val) return -2; /* not ready */ /* set the command/address... */ - smbus_write8(mmio, SMBHSTCMD, address & 0xff); + controller_write8(mmio, SMBHSTCMD, address & 0xff); /* set the device I'm talking to */ - smbus_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); + controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); /* output value */ - smbus_write8(mmio, SMBHSTDAT0, val); + controller_write8(mmio, SMBHSTDAT0, val); - byte = smbus_read8(mmio, SMBHSTCTRL); + byte = controller_read8(mmio, SMBHSTCTRL); byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - smbus_write8(mmio, SMBHSTCTRL, byte); + controller_write8(mmio, SMBHSTCTRL, byte); /* poll for transaction completion */ if (smbus_wait_until_done(mmio) < 0) |