diff options
Diffstat (limited to 'src/soc/amd/stoneyridge/include')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 29 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/southbridge.h | 59 |
2 files changed, 3 insertions, 85 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index e6327dc6db..7762043119 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -22,6 +22,9 @@ #define SPI_BASE_ADDRESS 0xfec10000 #define IO_APIC2_ADDR 0xfec20000 +/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ +#include <amdblocks/acpimmio_map.h> + /* I2C fixed address */ #define I2C_BASE_ADDRESS 0xfedc2000 #define I2C_DEVICE_SIZE 0x00001000 @@ -32,30 +35,6 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ -#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define ACPIMMIO_SM_PCI_BASE 0xfed80000 -#define ACPIMMIO_SMI_BASE 0xfed80200 -#define ACPIMMIO_PMIO_BASE 0xfed80300 -#define ACPIMMIO_PMIO2_BASE 0xfed80400 -#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 -#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 -#define ACPIMMIO_CMOS_BASE 0xfed80700 -#define ACPIMMIO_ACPI_BASE 0xfed80800 -#define ACPIMMIO_ASF_BASE 0xfed80900 -#define ACPIMMIO_SMBUS_BASE 0xfed80a00 -#define ACPIMMIO_WDT_BASE 0xfed80b00 -#define ACPIMMIO_HPET_BASE 0xfed80c00 -#define ACPIMMIO_IOMUX_BASE 0xfed80d00 -#define ACPIMMIO_MISC_BASE 0xfed80e00 -#define ACPIMMIO_DPVGA_BASE 0xfed81400 -#define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_GPIO1_BASE 0xfed81600 -#define ACPIMMIO_GPIO2_BASE 0xfed81700 -#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 -#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 -#define ACPIMMIO_AOAC_BASE 0xfed81e00 - #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 @@ -78,8 +57,6 @@ #define PM2_DATA 0xcd1 #define BIOSRAM_INDEX 0xcd4 #define BIOSRAM_DATA 0xcd5 -#define PM_INDEX 0xcd6 -#define PM_DATA 0xcd7 #define AB_INDX 0xcd8 #define AB_DATA (AB_INDX+4) #define SYS_RESET 0xcf9 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 618a5deff7..6734efb04d 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -483,7 +483,6 @@ void southbridge_final(void *chip_info); void southbridge_init(void *chip_info); void sb_lpc_port80(void); void sb_lpc_decode(void); -void sb_acpi_mmio_decode(void); void sb_pci_port80(void); void sb_read_mode(u32 mode); void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); @@ -491,66 +490,8 @@ void sb_tpm_decode(void); void sb_tpm_decode_spi(void); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); -uint8_t pm_io_read8(uint8_t reg); -uint16_t pm_io_read16(uint8_t reg); -uint32_t pm_io_read32(uint8_t reg); -void pm_io_write8(uint8_t reg, uint8_t value); -void pm_io_write16(uint8_t reg, uint16_t value); -void pm_io_write32(uint8_t reg, uint32_t value); -u8 pm_read8(u8 reg); -u16 pm_read16(u8 reg); -u32 pm_read32(u8 reg); -void pm_write8(u8 reg, u8 value); -void pm_write16(u8 reg, u16 value); -void pm_write32(u8 reg, u32 value); -u8 acpi_read8(u8 reg); -u16 acpi_read16(u8 reg); -u32 acpi_read32(u8 reg); -void acpi_write8(u8 reg, u8 value); -void acpi_write16(u8 reg, u16 value); -void acpi_write32(u8 reg, u32 value); -u8 misc_read8(u8 reg); -u16 misc_read16(u8 reg); -u32 misc_read32(u8 reg); -void misc_write8(u8 reg, u8 value); -void misc_write16(u8 reg, u16 value); -void misc_write32(u8 reg, u32 value); -uint8_t smi_read8(uint8_t offset); -uint16_t smi_read16(uint8_t offset); -uint32_t smi_read32(uint8_t offset); -void smi_write8(uint8_t offset, uint8_t value); -void smi_write16(uint8_t offset, uint16_t value); -void smi_write32(uint8_t offset, uint32_t value); -uint8_t biosram_read8(uint8_t offset); -void biosram_write8(uint8_t offset, uint8_t value); -uint16_t biosram_read16(uint8_t offset); -void biosram_write16(uint8_t offset, uint16_t value); -uint32_t biosram_read32(uint8_t offset); -void biosram_write32(uint8_t offset, uint32_t value); uint16_t pm_acpi_pm_cnt_blk(void); uint16_t pm_acpi_pm_evt_blk(void); -void xhci_pm_write8(uint8_t reg, uint8_t value); -uint8_t xhci_pm_read8(uint8_t reg); -void xhci_pm_write16(uint8_t reg, uint16_t value); -uint16_t xhci_pm_read16(uint8_t reg); -void xhci_pm_write32(uint8_t reg, uint32_t value); -uint32_t xhci_pm_read32(uint8_t reg); -u8 iomux_read8(u8 reg); -u16 iomux_read16(u8 reg); -u32 iomux_read32(u8 reg); -void iomux_write8(u8 reg, u8 value); -void iomux_write16(u8 reg, u16 value); -void iomux_write32(u8 reg, u32 value); -uint8_t asf_read8(uint8_t offset); -uint16_t asf_read16(uint8_t offset); -void asf_write8(uint8_t offset, uint8_t value); -void asf_write16(uint8_t offset, uint16_t value); -uint8_t smbus_read8(uint8_t offset); -uint16_t smbus_read16(uint8_t offset); -void smbus_write8(uint8_t offset, uint8_t value); -void smbus_write16(uint8_t offset, uint16_t value); -uint8_t aoac_read8(uint8_t reg); -void aoac_write8(uint8_t reg, uint8_t value); void bootblock_fch_early_init(void); void bootblock_fch_init(void); /** |