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-rw-r--r--src/soc/amd/stoneyridge/include/soc/gpio.h2
-rw-r--r--src/soc/amd/stoneyridge/include/soc/iomap.h22
2 files changed, 23 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 734074aad6..0854cf3d96 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -20,7 +20,7 @@
#define GPIO_DEVICE_DESC "GPIO Controller"
#ifndef __ACPI__
-#include <soc/amd/common/amd_defs.h>
+#include <soc/iomap.h>
#include <types.h>
#define GPIO_PIN_STS (1 << 16)
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
new file mode 100644
index 0000000000..d0c3f3e9d4
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Raptor Engineering, LLC
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_STONEYRIDGE_IOMAP_H__
+#define __SOC_STONEYRIDGE_IOMAP_H__
+
+#define AMD_SB_ACPI_MMIO_ADDR 0xfed80000ul
+
+#endif /* __SOC_STONEYRIDGE_IOMAP_H__ */