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-rw-r--r--src/soc/amd/stoneyridge/include/soc/nvs.h15
1 files changed, 7 insertions, 8 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index d296458399..eaaf1bdc39 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -14,14 +14,13 @@
struct __packed global_nvs {
/* Miscellaneous */
- uint8_t lids; /* 0x00 - LID State */
- uint32_t cbmc; /* 0x01 - 0x04 - coreboot Memory Console */
- uint64_t pm1i; /* 0x05 - 0x0c - System Wake Source - PM1 Index */
- uint64_t gpei; /* 0x0d - 0x14 - GPE Wake Source */
- uint8_t tmps; /* 0x15 - Temperature Sensor ID */
- uint8_t tcrt; /* 0x16 - Critical Threshold */
- uint8_t tpsv; /* 0x17 - Passive Threshold */
- uint8_t pad1[8];
+ uint32_t cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
+ uint64_t pm1i; /* 0x04 - 0x0b - System Wake Source - PM1 Index */
+ uint64_t gpei; /* 0x0c - 0x13 - GPE Wake Source */
+ uint8_t tmps; /* 0x14 - Temperature Sensor ID */
+ uint8_t tcrt; /* 0x15 - Critical Threshold */
+ uint8_t tpsv; /* 0x16 - Passive Threshold */
+ uint8_t pad1[9];
aoac_devs_t aoac; /* 0x20 - AOAC device enables */
uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */
uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */