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-rw-r--r--src/soc/amd/stoneyridge/include/soc/southbridge.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index 6734efb04d..0ac43857e5 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -357,12 +357,11 @@
#define LPC_WIDEIO2_GENERIC_PORT 0x90
#define SPIROM_BASE_ADDRESS_REGISTER 0xa0
-#define SPI_BASE_RESERVED (BIT(4) | BIT(5))
+#define SPI_BASE_ALIGNMENT BIT(6)
#define ROUTE_TPM_2_SPI BIT(3)
#define SPI_ABORT_ENABLE BIT(2)
#define SPI_ROM_ENABLE BIT(1)
#define SPI_ROM_ALT_ENABLE BIT(0)
-#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3))
/* LPC register 0xb8 is DWORD, here there are definitions for byte
access. For example, bits 31-24 are accessed through byte access