diff options
Diffstat (limited to 'src/soc/amd/stoneyridge/early_setup.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/early_setup.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index f1539eae52..c1a2978c0e 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -301,3 +301,51 @@ void hudson_tpm_decode_spi(void) pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, spibase | ROUTE_TPM_2_SPI); } + +/* + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The HUDSON power-on default is to map 512K ROM space. + * + */ +void hudson_enable_rom(void) +{ + u8 reg8; + pci_devfn_t dev; + + dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_io_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_io_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_io_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_io_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + */ + pci_io_write_config16(dev, 0x6c, 0x10000 + - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_io_write_config16(dev, 0x6e, 0xffff); +} + +void bootblock_fch_early_init(void) +{ + hudson_enable_rom(); + hudson_lpc_port80(); + hudson_lpc_decode(); +} |