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Diffstat (limited to 'src/soc/amd/stoneyridge/chip.h')
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h index 320bef0bdf..92223d1962 100644 --- a/src/soc/amd/stoneyridge/chip.h +++ b/src/soc/amd/stoneyridge/chip.h @@ -63,6 +63,15 @@ struct soc_amd_stoneyridge_config { u8 stapm_percent; u32 stapm_time_ms; u32 stapm_power_mw; + /* + * This specifies the LVDS/eDP power-up sequence time for the delay + * between VaryBL and BLON. + * 0 - Use the VBIOS default (default). The video BIOS default is 32ms. + * n - Values other than zero specify a setting of (4 * n) milliseconds + * time delay. + */ + u8 lvds_poseq_varybl_to_blon; + u8 lvds_poseq_blon_to_varybl; }; typedef struct soc_amd_stoneyridge_config config_t; |