diff options
Diffstat (limited to 'src/soc/amd/stoneyridge/bootblock/bootblock.c')
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock/bootblock.c | 78 |
1 files changed, 38 insertions, 40 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 8efe744384..473b118d11 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Intel Corporation.. + * Copyright (C) 2017 Advanced Micro Devices * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,52 +15,49 @@ */ #include <stdint.h> -#include <arch/io.h> -#include <device/pci_ids.h> -#include <soc/pci_devs.h> +#include <console/console.h> +#include <smp/node.h> +#include <bootblock_common.h> +#include <agesawrapper.h> +#include <agesawrapper_call.h> +#include <soc/hudson.h> -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The HUDSON power-on default is to map 512K ROM space. - * - */ -static void hudson_enable_rom(void) +asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - u8 reg8; - pci_devfn_t dev; + /* + * Call lib/bootblock.c main with BSP, shortcut for APs + * todo: rearchitect AGESA entry points to remove need + * to run amdinitreset, amdinitearly from bootblock. + * Remove AP shortcut. + */ + if (!boot_cpu()) + bootblock_soc_early_init(); /* APs will not return */ - dev = PCI_DEV(0, PCU_DEV, LPC_FUNC); + bootblock_main_with_timestamp(base_timestamp); +} - /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_io_read_config8(dev, 0x48); - reg8 |= (1 << 3) | (1 << 4); - pci_io_write_config8(dev, 0x48, reg8); +void bootblock_soc_early_init(void) +{ + amd_initmmio(); - /* LPC ROM address range 1: */ - /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_io_write_config16(dev, 0x68, 0x000e); - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_io_write_config16(dev, 0x6a, 0x000f); + if (!boot_cpu()) + bootblock_soc_init(); /* APs will not return */ - /* LPC ROM address range 2: */ - /* - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_io_write_config16(dev, 0x6c, 0x10000 - - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_io_write_config16(dev, 0x6e, 0xffff); + bootblock_fch_early_init(); + + post_code(0x90); + if (CONFIG_STONEYRIDGE_UART) + configure_hudson_uart(); } -static void bootblock_southbridge_init(void) +void bootblock_soc_init(void) { - hudson_enable_rom(); + u32 val = cpuid_eax(1); + printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + + post_code(0x37); + AGESAWRAPPER(amdinitreset); + + post_code(0x38); + AGESAWRAPPER(amdinitearly); /* APs will not exit amdinitearly */ } |