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-rw-r--r--src/soc/amd/sabrina/include/soc/msr.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/amd/sabrina/include/soc/msr.h b/src/soc/amd/sabrina/include/soc/msr.h
index bdc7a14c40..9dba2697e2 100644
--- a/src/soc/amd/sabrina/include/soc/msr.h
+++ b/src/soc/amd/sabrina/include/soc/msr.h
@@ -21,6 +21,10 @@
#define PSTATE_DEF_LO_FREQ_MUL_MASK (0xFF << PSTATE_DEF_LO_FREQ_MUL_SHIFT)
#define PSTATE_DEF_LO_CORE_FREQ_BASE 25
+/* Value defined in Serial VID Interface 3.0 spec (#56413, NDA only) */
+#define SERIAL_VID_DECODE_MICROVOLTS 5000
+#define SERIAL_VID_BASE_MICROVOLTS 245000L
+
#define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe7
#define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT 0xe8