diff options
Diffstat (limited to 'src/soc/amd/sabrina/cpu.c')
| -rw-r--r-- | src/soc/amd/sabrina/cpu.c | 16 |
1 files changed, 6 insertions, 10 deletions
diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index 462fb0d6fd..d4258a886f 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -2,6 +2,7 @@ /* TODO: Check if this is still correct */ +#include <acpi/acpi.h> #include <amdblocks/cpu.h> #include <amdblocks/mca.h> #include <amdblocks/reset.h> @@ -42,21 +43,12 @@ static void pre_mp_init(void) x86_mtrr_check(); } -static void post_mp_init(void) -{ - global_smi_enable(); - - /* SMMINFO only needs to be set up when booting from S5 */ - if (!acpi_is_wakeup_s3()) - apm_control(APM_CNT_SMMINFO); -} - static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = get_smm_info, .relocation_handler = smm_relocation_handler, - .post_mp_init = post_mp_init, + .post_mp_init = global_smi_enable, }; void mp_init_cpus(struct bus *cpu_bus) @@ -67,6 +59,10 @@ void mp_init_cpus(struct bus *cpu_bus) /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); } static void zen_2_3_init(struct device *dev) |