summaryrefslogtreecommitdiff
path: root/src/soc/amd/sabrina/acpi
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/amd/sabrina/acpi')
-rw-r--r--src/soc/amd/sabrina/acpi/globalnvs.asl22
-rw-r--r--src/soc/amd/sabrina/acpi/mmio.asl290
-rw-r--r--src/soc/amd/sabrina/acpi/pci0.asl86
-rw-r--r--src/soc/amd/sabrina/acpi/pci_int_defs.asl67
-rw-r--r--src/soc/amd/sabrina/acpi/rtc_workaround.asl28
-rw-r--r--src/soc/amd/sabrina/acpi/soc.asl43
6 files changed, 536 insertions, 0 deletions
diff --git a/src/soc/amd/sabrina/acpi/globalnvs.asl b/src/soc/amd/sabrina/acpi/globalnvs.asl
new file mode 100644
index 0000000000..19d58d5ec5
--- /dev/null
+++ b/src/soc/amd/sabrina/acpi/globalnvs.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/* TODO: Check if this is still correct */
+
+/*
+ * NOTE: The layout of the GNVS structure below must match the layout in
+ * soc/amd/sabrina/include/soc/nvs.h !!!
+ */
+
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Miscellaneous */
+ , 8, // 0x00 - Processor Count
+ LIDS, 8, // 0x01 - LID State
+ , 8, // 0x02 - AC Power State
+ CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console
+ PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index
+ GPEI, 64, // 0x0f - 0x16 - GPE Wake Source
+ TMPS, 8, // 0x17 - Temperature Sensor ID
+ TCRT, 8, // 0x18 - Critical Threshold
+ TPSV, 8, // 0x19 - Passive Threshold
+}
diff --git a/src/soc/amd/sabrina/acpi/mmio.asl b/src/soc/amd/sabrina/acpi/mmio.asl
new file mode 100644
index 0000000000..381405f91e
--- /dev/null
+++ b/src/soc/amd/sabrina/acpi/mmio.asl
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Check if this is still correct */
+
+#include <soc/amd/common/acpi/aoac.asl>
+#include <soc/aoac_defs.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <amdblocks/acpimmio_map.h>
+
+Device (AAHB)
+{
+ Name (_HID, "AAHB0000")
+ Name (_UID, 0x0)
+ Name (_CRS, ResourceTemplate()
+ {
+ Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
+ })
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (GPIO)
+{
+ Name (_HID, GPIO_DEVICE_NAME)
+ Name (_CID, GPIO_DEVICE_NAME)
+ Name (_UID, 0)
+ Name (_DDN, GPIO_DEVICE_DESC)
+
+ Method (_CRS, 0) {
+ Local0 = ResourceTemplate() {
+ Interrupt (
+ ResourceConsumer,
+ Level,
+ ActiveLow,
+ Shared, , , IRQR)
+ { 0 }
+ Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+ }
+ CreateDWordField (Local0, IRQR._INT, IRQN)
+ If (PICM) {
+ IRQN = IGPI
+ } Else {
+ IRQN = PGPI
+ }
+ If (IRQN == 0x1f) {
+ Return (ResourceTemplate() {
+ Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
+ })
+ } Else {
+ Return (Local0)
+ }
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
+
+Device (FUR0)
+{
+ Name (_HID, "AMDI0020")
+ Name (_UID, 0x0)
+ Method (_CRS, 0) {
+ Local0 = ResourceTemplate() {
+ Interrupt (
+ ResourceConsumer,
+ Edge,
+ ActiveHigh,
+ Exclusive, , , IRQR)
+ { 0 }
+ Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+ }
+ CreateDWordField (Local0, IRQR._INT, IRQN)
+ If (PICM) {
+ IRQN = IUA0
+ } Else {
+ IRQN = PUA0
+ }
+ If (IRQN == 0x1f) {
+ Return (ResourceTemplate() {
+ Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
+ })
+ } Else {
+ Return (Local0)
+ }
+ }
+
+ AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0)
+}
+
+Device (FUR1) {
+ Name (_HID, "AMDI0020")
+ Name (_UID, 0x1)
+ Method (_CRS, 0) {
+ Local0 = ResourceTemplate() {
+ Interrupt (
+ ResourceConsumer,
+ Edge,
+ ActiveHigh,
+ Exclusive, , , IRQR)
+ { 0 }
+ Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+ }
+ CreateDWordField (Local0, IRQR._INT, IRQN)
+ If (PICM) {
+ IRQN = IUA1
+ } Else {
+ IRQN = PUA1
+ }
+ If (IRQN == 0x1f) {
+ Return (ResourceTemplate() {
+ Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
+ })
+ } Else {
+ Return (Local0)
+ }
+ }
+
+ AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0)
+}
+
+Device (I2C0) {
+ Name (_HID, "AMDI0010")
+ Name (_UID, 0x0)
+ Method (_CRS, 0) {
+ Local0 = ResourceTemplate() {
+ Interrupt (
+ ResourceConsumer,
+ Edge,
+ ActiveHigh,
+ Exclusive, , , IRQR)
+ { 0 }
+ Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+ }
+ CreateDWordField (Local0, IRQR._INT, IRQN)
+ If (PICM) {
+ IRQN = II20
+ } Else {
+ IRQN = PI20
+ }
+ If (IRQN == 0x1f) {
+ Return (ResourceTemplate() {
+ Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
+ })
+ } Else {
+ Return (Local0)
+ }
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0)
+}
+
+Device (I2C1) {
+ Name (_HID, "AMDI0010")
+ Name (_UID, 0x1)
+ Method (_CRS, 0) {
+ Local0 = ResourceTemplate() {
+ Interrupt (
+ ResourceConsumer,
+ Edge,
+ ActiveHigh,
+ Exclusive, , , IRQR)
+ { 0 }
+ Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+ }
+ CreateDWordField (Local0, IRQR._INT, IRQN)
+ If (PICM) {
+ IRQN = II21
+ } Else {
+ IRQN = PI21
+ }
+ If (IRQN == 0x1f) {
+ Return (ResourceTemplate() {
+ Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
+ })
+ } Else {
+ Return (Local0)
+ }
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0)
+}
+
+Device (I2C2) {
+ Name (_HID, "AMDI0010")
+ Name (_UID, 0x2)
+ Method (_CRS, 0) {
+ Local0 = ResourceTemplate() {
+ Interrupt (
+ ResourceConsumer,
+ Edge,
+ ActiveHigh,
+ Exclusive, , , IRQR)
+ { 0 }
+ Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+ }
+ CreateDWordField (Local0, IRQR._INT, IRQN)
+ If (PICM) {
+ IRQN = II22
+ } Else {
+ IRQN = PI22
+ }
+ If (IRQN == 0x1f) {
+ Return (ResourceTemplate() {
+ Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
+ })
+ } Else {
+ Return (Local0)
+ }
+ }
+
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0)
+}
+
+Device (I2C3)
+{
+ Name (_HID, "AMDI0010")
+ Name (_UID, 0x3)
+ Method (_CRS, 0) {
+ Local0 = ResourceTemplate() {
+ Interrupt (
+ ResourceConsumer,
+ Edge,
+ ActiveHigh,
+ Exclusive, , , IRQR)
+ { 0 }
+ Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+ }
+ CreateDWordField (Local0, IRQR._INT, IRQN)
+ If (PICM) {
+ IRQN = II23
+ } Else {
+ IRQN = PI23
+ }
+ If (IRQN == 0x1f) {
+ Return (ResourceTemplate() {
+ Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
+ })
+ } Else {
+ Return (Local0)
+ }
+ }
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0)
+}
+
+Device (MISC)
+{
+ Name (_HID, "AMD0040")
+ Name (_UID, 0x3)
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
+ })
+ Name (_DSD, Package ()
+ {
+ ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package ()
+ {
+ Package () { "is-rv", 1 },
+ },
+ })
+ Method (_STA, 0x0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/soc/amd/sabrina/acpi/pci0.asl b/src/soc/amd/sabrina/acpi/pci0.asl
new file mode 100644
index 0000000000..853c686de0
--- /dev/null
+++ b/src/soc/amd/sabrina/acpi/pci0.asl
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Check if this is still correct */
+
+Device(PCI0) {
+ Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */
+ Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */
+ External(TOM1, IntObj) /* Generated by root_complex.c */
+
+ Method(_BBN, 0, NotSerialized) {
+ Return(Zero) /* Bus number = 0 */
+ }
+
+ Method(_STA, 0, NotSerialized) {
+ Return(0x0B) /* Status is visible */
+ }
+
+ /* Operating System Capabilities Method */
+ Method(_OSC, 4) {
+ CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */
+
+ /* Check for proper PCI/PCIe UUID */
+ If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) {
+ /* Let OS control everything */
+ Return (Arg3)
+ } Else {
+ CDW1 |= 4 /* Unrecognized UUID */
+ Return (Arg3)
+ }
+ }
+ Name(CRES, ResourceTemplate() {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x00ff, /* range maximum */
+ 0x0000, /* translation */
+ 0x0100, /* length */
+ ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */
+
+ IO(Decode16, 0x0cf8, 0x0cf8, 1, 8)
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0000, /* range minimum */
+ 0x0cf7, /* range maximum */
+ 0x0000, /* translation */
+ 0x0cf8 /* length */
+ )
+
+ WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, /* address granularity */
+ 0x0d00, /* range minimum */
+ 0xffff, /* range maximum */
+ 0x0000, /* translation */
+ 0xf300 /* length */
+ )
+
+ Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */
+ Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */
+
+ /* memory space for PCI BARs below 4GB */
+ Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO)
+ })
+
+ Method(_CRS, 0) {
+ CreateDWordField(CRES, ^MMIO._BAS, MM1B)
+ CreateDWordField(CRES, ^MMIO._LEN, MM1L)
+
+ /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
+ MM1B = TOM1
+ Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
+ Local0 -= TOM1
+ MM1L = Local0
+
+ CreateWordField(CRES, ^PSB0._MAX, BMAX)
+ CreateWordField(CRES, ^PSB0._LEN, BLEN)
+ BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
+ BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
+
+ Return(CRES) /* note to change the Name buffer */
+ } /* end of Method(_SB.PCI0._CRS) */
+
+ /* 0:14.3 - LPC */
+ #include <soc/amd/common/acpi/lpc.asl>
+
+} /* End PCI0 scope */
diff --git a/src/soc/amd/sabrina/acpi/pci_int_defs.asl b/src/soc/amd/sabrina/acpi/pci_int_defs.asl
new file mode 100644
index 0000000000..e0d1fa2a94
--- /dev/null
+++ b/src/soc/amd/sabrina/acpi/pci_int_defs.asl
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Check if this is still correct */
+
+/* PCI IRQ mapping registers, C00h-C01h. */
+OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
+ Field(PRQM, ByteAcc, NoLock, Preserve) {
+ PRQI, 0x00000008,
+ PRQD, 0x00000008, /* Offset: 1h */
+}
+/*
+ * All PIC indexes are prefixed with P.
+ * All IO-APIC indexes are prefixed with I.
+ */
+IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
+ PIRA, 0x00000008, /* Index 0: INTA */
+ PIRB, 0x00000008, /* Index 1: INTB */
+ PIRC, 0x00000008, /* Index 2: INTC */
+ PIRD, 0x00000008, /* Index 3: INTD */
+ PIRE, 0x00000008, /* Index 4: INTE */
+ PIRF, 0x00000008, /* Index 5: INTF */
+ PIRG, 0x00000008, /* Index 6: INTG */
+ PIRH, 0x00000008, /* Index 7: INTH */
+
+ Offset (0x43),
+ PMMC, 0x00000008, /* Index 0x43: eMMC */
+
+ Offset (0x62),
+ PGPI, 0x00000008, /* Index 0x62: GPIO */
+
+ Offset (0x70),
+ PI20, 0x00000008, /* Index 0x70: I2C0 */
+ PI21, 0x00000008, /* Index 0x71: I2C1 */
+ PI22, 0x00000008, /* Index 0x72: I2C2 */
+ PI23, 0x00000008, /* Index 0x73: I2C3 */
+ PUA0, 0x00000008, /* Index 0x74: UART0 */
+ PUA1, 0x00000008, /* Index 0x75: UART1 */
+ PI24, 0x00000008, /* Index 0x76: I2C4 */
+ PI25, 0x00000008, /* Index 0x77: I2C5 */
+
+ /* IO-APIC IRQs */
+ Offset (0x80),
+ IORA, 0x00000008, /* Index 0x80: INTA */
+ IORB, 0x00000008, /* Index 0x81: INTB */
+ IORC, 0x00000008, /* Index 0x82: INTC */
+ IORD, 0x00000008, /* Index 0x83: INTD */
+ IORE, 0x00000008, /* Index 0x84: INTE */
+ IORF, 0x00000008, /* Index 0x85: INTF */
+ IORG, 0x00000008, /* Index 0x86: INTG */
+ IORH, 0x00000008, /* Index 0x87: INTH */
+
+ Offset (0xC3),
+ IMMC, 0x00000008, /* Index 0xC3: eMMC */
+
+ Offset (0xE2),
+ IGPI, 0x00000008, /* Index 0xE2: GPIO */
+
+ Offset (0xF0),
+ II20, 0x00000008, /* Index 0xF0: I2C0 */
+ II21, 0x00000008, /* Index 0xF1: I2C1 */
+ II22, 0x00000008, /* Index 0xF2: I2C2 */
+ II23, 0x00000008, /* Index 0xF3: I2C3 */
+ IUA0, 0x00000008, /* Index 0xF4: UART0 */
+ IUA1, 0x00000008, /* Index 0xF5: UART1 */
+ II24, 0x00000008, /* Index 0xF6: I2C4 */
+ II25, 0x00000008, /* Index 0xF7: I2C5 */
+}
diff --git a/src/soc/amd/sabrina/acpi/rtc_workaround.asl b/src/soc/amd/sabrina/acpi/rtc_workaround.asl
new file mode 100644
index 0000000000..8bbca4e3f1
--- /dev/null
+++ b/src/soc/amd/sabrina/acpi/rtc_workaround.asl
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Check if this is still correct */
+
+/*
+ * Workaround for RTC on Cezanne.
+ * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/platform/x86/amd-pmc.c;l=416;drc=54a96af06ae6851e4a02e8dd700de0d579ef7839
+ */
+
+Scope (\_SB.PEP) {
+ Name (_PRW, Package () {
+ Package() {\_SB.GPIO, 0},
+ 0x03
+ })
+}
+
+Scope (\_SB.GPIO) {
+ Name (_AEI, ResourceTemplate () {
+ GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPIO",,,,)
+ {
+ 44 /* int_shdwsysalarmfire */
+ }
+ })
+
+ Method (_E2C, 0, Serialized) {
+ Notify (\_SB_.PEP, 0x02)
+ }
+}
diff --git a/src/soc/amd/sabrina/acpi/soc.asl b/src/soc/amd/sabrina/acpi/soc.asl
new file mode 100644
index 0000000000..f5a41a17cf
--- /dev/null
+++ b/src/soc/amd/sabrina/acpi/soc.asl
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* TODO: Check if this is still correct */
+
+#include "globalnvs.asl"
+
+Scope(\_SB) {
+ /* global utility methods expected within the \_SB scope */
+ #include <arch/x86/acpi/globutil.asl>
+
+ #include <soc/amd/common/acpi/gpio_bank_lib.asl>
+
+ #include <soc/amd/common/acpi/osc.asl>
+
+ #include "pci_int_defs.asl"
+
+ #include <soc/amd/common/acpi/pci_int.asl>
+
+ #include "mmio.asl"
+
+ #include "pci0.asl"
+} /* End \_SB scope */
+
+#include <soc/amd/common/acpi/alib.asl>
+
+#include <soc/amd/common/acpi/platform.asl>
+
+#include <soc/amd/common/acpi/sleepstates.asl>
+
+#include <soc/amd/common/acpi/upep.asl>
+
+#include "rtc_workaround.asl"
+
+/*
+ * Platform Wake Notify
+ *
+ * This is called by soc/amd/common/acpi/platform.asl.
+ */
+Method (PNOT)
+{
+ /* Report AC/DC state to ALIB using WAL1() */
+ \WAL1 ()
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 06:08:45 +0000