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-rw-r--r--src/soc/amd/picasso/include/soc/smi.h3
-rw-r--r--src/soc/amd/picasso/psp.c39
-rw-r--r--src/soc/amd/picasso/smi.c3
-rw-r--r--src/soc/amd/picasso/smihandler.c4
4 files changed, 49 insertions, 0 deletions
diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h
index e890e1319a..fb8061ca16 100644
--- a/src/soc/amd/picasso/include/soc/smi.h
+++ b/src/soc/amd/picasso/include/soc/smi.h
@@ -86,6 +86,7 @@
#define SMITYPE_NB_GPP_HOT_PLUG 30
/* 31 Reserved */
#define SMITYPE_WAKE_L2 32
+#define SMITYPE_PSP 33
/* 33 - 38 Reserved */
#define SMITYPE_AZPME 39
#define SMITYPE_USB_PD_I2C4 40
@@ -186,6 +187,8 @@
#define SMI_REG_CONTROL8 0xc0
#define SMI_REG_CONTROL9 0xc4
+#define SMI_MODE_MASK 0x03
+
enum smi_mode {
SMI_MODE_DISABLE = 0,
SMI_MODE_SMI = 1,
diff --git a/src/soc/amd/picasso/psp.c b/src/soc/amd/picasso/psp.c
index d6eb7d31a3..88b25b88b0 100644
--- a/src/soc/amd/picasso/psp.c
+++ b/src/soc/amd/picasso/psp.c
@@ -3,6 +3,8 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
+#include <soc/smi.h>
+#include <amdblocks/acpimmio_map.h>
#include <amdblocks/psp.h>
#define PSP_MAILBOX_OFFSET 0x10570
@@ -20,3 +22,40 @@ void *soc_get_mbox_address(void)
return (void *)(psp_mmio + PSP_MAILBOX_OFFSET);
}
+
+void soc_fill_smm_trig_info(struct smm_trigger_info *trig)
+{
+ if (!trig)
+ return;
+
+ trig->address = 0xfed802a8;
+ trig->address_type = SMM_TRIGGER_MEM;
+ trig->value_width = SMM_TRIGGER_DWORD;
+ trig->value_and_mask = 0xfdffffff;
+ trig->value_or_mask = 0x02000000;
+}
+
+void soc_fill_smm_reg_info(struct smm_register_info *reg)
+{
+ if (!reg)
+ return;
+
+ reg->smi_enb.address = ACPIMMIO_SMI_BASE + SMI_REG_SMITRIG0;
+ reg->smi_enb.address_type = SMM_TRIGGER_MEM;
+ reg->smi_enb.value_width = SMM_TRIGGER_DWORD;
+ reg->smi_enb.reg_bit_mask = SMITRG0_SMIENB;
+ reg->smi_enb.expect_value = 0;
+
+ reg->eos.address = ACPIMMIO_SMI_BASE + SMI_REG_SMITRIG0;
+ reg->eos.address_type = SMM_TRIGGER_MEM;
+ reg->eos.value_width = SMM_TRIGGER_DWORD;
+ reg->eos.reg_bit_mask = SMITRG0_EOS;
+ reg->eos.expect_value = SMITRG0_EOS;
+
+ reg->psp_smi_en.address = ACPIMMIO_SMI_BASE + SMI_REG_CONTROL0;
+ reg->psp_smi_en.address += sizeof(uint32_t) * SMITYPE_PSP / 16;
+ reg->psp_smi_en.address_type = SMM_TRIGGER_MEM;
+ reg->psp_smi_en.value_width = SMM_TRIGGER_DWORD;
+ reg->psp_smi_en.reg_bit_mask = SMI_MODE_MASK << (2 * SMITYPE_PSP % 16);
+ reg->psp_smi_en.expect_value = SMI_MODE_SMI << (2 * SMITYPE_PSP % 16);
+}
diff --git a/src/soc/amd/picasso/smi.c b/src/soc/amd/picasso/smi.c
index ab8f405e59..273c55b635 100644
--- a/src/soc/amd/picasso/smi.c
+++ b/src/soc/amd/picasso/smi.c
@@ -17,6 +17,7 @@
* Utilities for SMM setup
*/
+#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <amdblocks/acpimmio.h>
@@ -35,4 +36,6 @@ void enable_smi_generation(void)
reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */
reg |= SMITRG0_EOS; /* Set EOS bit */
smi_write32(SMI_REG_SMITRIG0, reg);
+
+ outb(APM_CNT_SMMINFO, APM_CNT);
}
diff --git a/src/soc/amd/picasso/smihandler.c b/src/soc/amd/picasso/smihandler.c
index 55493776dd..e4d1c86f57 100644
--- a/src/soc/amd/picasso/smihandler.c
+++ b/src/soc/amd/picasso/smihandler.c
@@ -26,6 +26,7 @@
#include <soc/southbridge.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/acpi.h>
+#include <amdblocks/psp.h>
#include <elog.h>
/* bits in smm_io_trap */
@@ -125,6 +126,9 @@ static void sb_apmc_smi_handler(void)
if (CONFIG(SMMSTORE))
southbridge_smi_store();
break;
+ case APM_CNT_SMMINFO:
+ psp_notify_smm();
+ break;
}
mainboard_smi_apmc(cmd);