diff options
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/amd/picasso/memlayout.ld | 7 | ||||
| -rw-r--r-- | src/soc/amd/picasso/memlayout_psp_verstage.ld | 62 | ||||
| -rw-r--r-- | src/soc/amd/picasso/memlayout_transfer_buffer.inc | 19 | ||||
| -rw-r--r-- | src/soc/amd/picasso/memlayout_x86.ld | 116 |
5 files changed, 1 insertions, 208 deletions
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d7d2a6c1a..6fa36641cd 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_LFENCE select UDELAY_TSC select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO @@ -57,10 +58,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS -config MEMLAYOUT_LD_FILE - string - default "src/soc/amd/picasso/memlayout.ld" - config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/picasso/memlayout.ld deleted file mode 100644 index 6f5d4cf82f..0000000000 --- a/src/soc/amd/picasso/memlayout.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if ENV_SEPARATE_VERSTAGE && CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) - #include "memlayout_psp_verstage.ld" -#else - #include "memlayout_x86.ld" -#endif /* ENV_SEPARATE_VERSTAGE && CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) */ diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/picasso/memlayout_psp_verstage.ld deleted file mode 100644 index ca95cf81bd..0000000000 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <memlayout.h> -#include <soc/psp_transfer.h> -#include <fmap_config.h> - -/* - * Start of available space is 0x15000 and this is where the - * header for the user app (verstage) must be mapped. - * Size is 0x28000 bytes - */ -#define PSP_SRAM_START 0x15000 -#define PSP_SRAM_SIZE 160K - -#define VERSTAGE_START 0x15000 - -/* - * The temp stack can be made much smaller if needed - even 256 bytes - * should be sufficient. This is just for the function mapping the - * actual stack. - */ -#define PSP_VERSTAGE_TEMP_STACK_START 0x32000 -#define PSP_VERSTAGE_TEMP_STACK_SIZE 4K - -/* - * The top of the stack must be 4k aligned, so set the bottom as 4k aligned - * and make the size a multiple of 4k - */ -#define PSP_VERSTAGE_STACK_START 0x33000 -#define PSP_VERSTAGE_STACK_SIZE 40K - -ENTRY(_psp_vs_start) -SECTIONS -{ - SRAM_START(PSP_SRAM_START) - _verstage = .; - - .text : { *(PSP_HEADER_DATA) } - .text : { *(.text._psp_vs_start) } - .text : { *(.text.Main) } - .text : { *(.text*) } - .rodata : { *(.rodata*) } - - .data : { *(.data*) } - .data : { *(PSP_FOOTER_DATA) } - - _bss_start = .; - .bss : { *(.bss*) } - _bss_end = .; - - ALIGN_COUNTER(64) - _everstage = .; - - #include "memlayout_transfer_buffer.inc" - - PSP_VERSTAGE_TEMP_STACK_END = (PSP_VERSTAGE_TEMP_STACK_START + PSP_VERSTAGE_TEMP_STACK_SIZE ); - - REGION(stack, PSP_VERSTAGE_STACK_START, PSP_VERSTAGE_STACK_SIZE, 64) - PSP_VERSTAGE_STACK_BASE = _stack; - PSP_VERSTAGE_STACK_END = _estack; - SRAM_END(PSP_SRAM_START + PSP_SRAM_SIZE) -} diff --git a/src/soc/amd/picasso/memlayout_transfer_buffer.inc b/src/soc/amd/picasso/memlayout_transfer_buffer.inc deleted file mode 100644 index a88e81ac32..0000000000 --- a/src/soc/amd/picasso/memlayout_transfer_buffer.inc +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#if CONFIG(VBOOT) - ALIGN_COUNTER(64) - _transfer_buffer = .; - REGION(transfer_info, ., TRANSFER_INFO_SIZE, 4) - - ALIGN_COUNTER(64) - VBOOT2_WORK(., VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) -#endif - - ALIGN_COUNTER(64) - PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) - TIMESTAMP(., TIMESTAMP_BUFFER_SIZE) - FMAP_CACHE(., FMAP_SIZE) - -#if CONFIG(VBOOT) - _etransfer_buffer = .; -#endif diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/picasso/memlayout_x86.ld deleted file mode 100644 index 369d43151e..0000000000 --- a/src/soc/amd/picasso/memlayout_x86.ld +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <memlayout.h> -#include <arch/header.ld> -#include <soc/psp_transfer.h> - -#define EARLY_RESERVED_DRAM_START(addr) SYMBOL(early_reserved_dram, addr) -#define EARLY_RESERVED_DRAM_END(addr) SYMBOL(eearly_reserved_dram, addr) - -#define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr) -#define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr) - -/* - * - * +--------------------------------+ - * | | - * | | - * | | - * | | - * | | - * | | - * | | - * reserved_dram_end +--------------------------------+ - * | | - * | verstage (if reqd) | - * | (VERSTAGE_SIZE) | - * +--------------------------------+ VERSTAGE_ADDR - * | | - * | FSP-M | - * | (FSP_M_SIZE) | - * +--------------------------------+ FSP_M_ADDR - * | |X86_RESET_VECTOR = ROMSTAGE_ADDR + ROMSTAGE_SIZE - 0x10 - * | romstage | - * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | bootblock | - * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR - * | Unused hole | - * +--------------------------------+ - * | FMAP cache (FMAP_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 - * | Early Timestamp region (512B) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE - * | Preram CBMEM console | - * | (PRERAM_CBMEM_CONSOLE_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE - * | PSP shared (vboot workbuf) | - * |(VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE) | - * +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 - * | Transfer Info Structure | - * +--------------------------------+ PSP_SHAREDMEM_BASE - * | APOB (64KiB) | - * +--------------------------------+ PSP_APOB_DRAM_ADDRESS - * | Early BSP stack | - * | (EARLYRAM_BSP_STACK_SIZE) | - * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE - * | DRAM | - * +--------------------------------+ 0x100000 - * | Option ROM | - * +--------------------------------+ 0xc0000 - * | Legacy VGA | - * +--------------------------------+ 0xa0000 - * | DRAM | - * +--------------------------------+ 0x0 - */ -SECTIONS -{ - DRAM_START(0x0) - - EARLY_RESERVED_DRAM_START(CONFIG_EARLY_RESERVED_DRAM_BASE) - - EARLYRAM_STACK(., CONFIG_EARLYRAM_BSP_STACK_SIZE) - REGION(apob, CONFIG_PSP_APOB_DRAM_ADDRESS, 64K, 1) - -#if CONFIG(VBOOT) - PSP_SHAREDMEM_DRAM_START(CONFIG_PSP_SHAREDMEM_BASE) -#endif - -#include "memlayout_transfer_buffer.inc" - -#if CONFIG(VBOOT) - PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) -#endif - _ = ASSERT((CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10) == CONFIG_X86_RESET_VECTOR, "Reset vector should be -0x10 from end of bootblock"); - _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); - BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) - ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) - REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) -#if CONFIG(VBOOT_SEPARATE_VERSTAGE) - VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) -#endif - - EARLY_RESERVED_DRAM_END(.) - - RAMSTAGE(CONFIG_RAMBASE, 8M) -} - -#if ENV_BOOTBLOCK - -gdtptr16_offset = gdtptr16 & 0xffff; -nullidt_offset = nullidt & 0xffff; - -SECTIONS { - /* Trigger an error if I have an unusable start address */ - _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; - _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - - . = CONFIG_X86_RESET_VECTOR; - .reset . : { - *(.reset); - . = 15; - BYTE(0x00); - } -} -#endif /* ENV_BOOTBLOCK */ |