diff options
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/bootblock.c | 22 |
1 files changed, 1 insertions, 21 deletions
diff --git a/src/soc/amd/picasso/bootblock.c b/src/soc/amd/picasso/bootblock.c index 0b52a17307..7d1f01cec8 100644 --- a/src/soc/amd/picasso/bootblock.c +++ b/src/soc/amd/picasso/bootblock.c @@ -2,12 +2,12 @@ #include <stdint.h> #include <symbols.h> +#include <amdblocks/cpu.h> #include <amdblocks/reset.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> -#include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/tsc.h> @@ -16,9 +16,6 @@ #include <soc/southbridge.h> #include <soc/i2c.h> #include <amdblocks/amd_pci_mmconf.h> -#include <acpi/acpi.h> - -asmlinkage void bootblock_resume_entry(void); /* PSP performs the memory training and setting up DRAM map prior to x86 cores being released. Honor TOP_MEM and set up caching from 0 til TOP_MEM. Likewise, @@ -91,23 +88,6 @@ static void set_caching(void) enable_cache(); } -static void write_resume_eip(void) -{ - msr_t s3_resume_entry = { - .hi = (uint64_t)(uintptr_t)bootblock_resume_entry >> 32, - .lo = (uintptr_t)bootblock_resume_entry & 0xffffffff, - }; - - /* - * Writing to the EIP register can only be done once, otherwise a fault is triggered. - * When this register is written, it will trigger the microcode to stash the CPU state - * (crX , mtrrs, registers, etc) into the CC6 save area. On resume, the state will be - * restored and execution will continue at the EIP. - */ - if (!acpi_is_wakeup_s3()) - wrmsr(S3_RESUME_EIP_MSR, s3_resume_entry); -} - asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { set_caching(); |