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-rw-r--r--src/soc/amd/picasso/include/soc/southbridge.h16
-rw-r--r--src/soc/amd/picasso/uart.c57
2 files changed, 0 insertions, 73 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index 220d92ea7a..c7f30e24ec 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -13,14 +13,6 @@
* - fixed addresses offset from 0xfed80000
*/
-/* SMBus controller registers: 0xfed80000 or D14F0 */
-#define SMB_UART_CONFIG 0xfc
-#define SMB_UART3_1_8M BIT(31) /* defaults are 0 = 48MHz */
-#define SMB_UART2_1_8M BIT(30)
-#define SMB_UART1_1_8M BIT(29)
-#define SMB_UART0_1_8M BIT(28)
-#define SMB_UART_1_8M_SHIFT 28
-
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
#define PM_PCI_CTRL 0x08
#define FORCE_SLPSTATE_RETRY BIT(25)
@@ -144,13 +136,6 @@
#define FCH_AOAC_DEV_ESPI 27
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
-#define FCH_LEGACY_UART_MAP_SHIFT 8
-#define FCH_LEGACY_UART_MAP_SIZE 2
-#define FCH_LEGACY_UART_MAP_MASK 0x3
-#define FCH_LEGACY_UART_RANGE_2E8 0
-#define FCH_LEGACY_UART_RANGE_2F8 1
-#define FCH_LEGACY_UART_RANGE_3E8 2
-#define FCH_LEGACY_UART_RANGE_3F8 3
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
@@ -196,7 +181,6 @@ void southbridge_final(void *chip_info);
void southbridge_init(void *chip_info);
void fch_pre_init(void);
void fch_early_init(void);
-void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx);
/* Initialize all the i2c buses that are marked with early init. */
void i2c_soc_early_init(void);
diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c
index b417051b97..472a0be7d5 100644
--- a/src/soc/amd/picasso/uart.c
+++ b/src/soc/amd/picasso/uart.c
@@ -5,7 +5,6 @@
#include <commonlib/helpers.h>
#include <device/mmio.h>
#include <amdblocks/gpio_banks.h>
-#include <amdblocks/acpimmio.h>
#include <amdblocks/aoac.h>
#include <soc/southbridge.h>
#include <soc/gpio.h>
@@ -42,71 +41,17 @@ uintptr_t get_uart_base(unsigned int idx)
return uart_info[idx].base;
}
-static bool get_uart_idx(uintptr_t base, unsigned int *idx)
-{
- for (unsigned int i = 0; i < ARRAY_SIZE(uart_info); i++) {
- if (base == uart_info[i].base) {
- *idx = i;
- return true;
- }
- }
-
- return false;
-}
-
void clear_uart_legacy_config(void)
{
write16((void *)FCH_LEGACY_UART_DECODE, 0);
}
-void set_uart_legacy_config(unsigned int uart_idx, unsigned int range_idx)
-{
- uint16_t uart_legacy_decode;
- uint8_t uart_map_offset;
-
- if (uart_idx >= ARRAY_SIZE(uart_info) || range_idx >= ARRAY_SIZE(uart_info))
- return;
-
- uart_legacy_decode = read16((void *)FCH_LEGACY_UART_DECODE);
- /* Map uart_idx to io range_idx */
- uart_map_offset = range_idx * FCH_LEGACY_UART_MAP_SIZE + FCH_LEGACY_UART_MAP_SHIFT;
- uart_legacy_decode &= ~(FCH_LEGACY_UART_MAP_MASK << uart_map_offset);
- uart_legacy_decode |= uart_idx << uart_map_offset;
- /* Enable io range */
- uart_legacy_decode |= 1 << range_idx;
- write16((void *)FCH_LEGACY_UART_DECODE, uart_legacy_decode);
-}
-
-static void enable_uart_legacy_decode(uintptr_t base)
-{
- unsigned int idx;
- const uint8_t range_idx[ARRAY_SIZE(uart_info)] = {
- FCH_LEGACY_UART_RANGE_3F8,
- FCH_LEGACY_UART_RANGE_2F8,
- FCH_LEGACY_UART_RANGE_3E8,
- FCH_LEGACY_UART_RANGE_2E8,
- };
-
- if (get_uart_idx(base, &idx)) {
- set_uart_legacy_config(idx, range_idx[idx]);
- }
-}
-
void set_uart_config(unsigned int idx)
{
- uint32_t uart_ctrl;
-
if (idx >= ARRAY_SIZE(uart_info))
return;
program_gpios(uart_info[idx].mux, 2);
-
- if (CONFIG(AMD_SOC_UART_1_8MZ)) {
- uart_ctrl = sm_pci_read32(SMB_UART_CONFIG);
- uart_ctrl |= 1 << (SMB_UART_1_8M_SHIFT + idx);
- sm_pci_write32(SMB_UART_CONFIG, uart_ctrl);
- }
-
}
static const char *uart_acpi_name(const struct device *dev)
@@ -151,8 +96,6 @@ static void uart_enable(struct device *dev)
if (dev->enabled) {
power_on_aoac_device(dev_id);
wait_for_aoac_enabled(dev_id);
- if (CONFIG(AMD_SOC_UART_LEGACY))
- enable_uart_legacy_decode(dev->path.mmio.addr);
} else {
power_off_aoac_device(dev_id);
}