diff options
Diffstat (limited to 'src/soc/amd/picasso/tsc_freq.c')
| -rw-r--r-- | src/soc/amd/picasso/tsc_freq.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index 29121b955e..6167726955 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -19,31 +19,27 @@ #include <cpu/amd/msr.h> #include <cpu/x86/tsc.h> #include <console/console.h> -#include <soc/pci_devs.h> -#include <device/pci_ops.h> + +static unsigned long mhz; unsigned long tsc_freq_mhz(void) { msr_t msr; uint8_t cpufid; uint8_t cpudid; - uint8_t boost_states; + uint8_t high_state; - /* - * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for - * MSR0000_0010. The TSC increments at the P0 frequency. According - * to the "Software P-state Numbering" section, P0 is the highest - * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). - */ - boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) - >> 2) & 0x7; + if (mhz) + return mhz; - msr = rdmsr(PSTATE_0_MSR + boost_states); + high_state = rdmsr(PS_LIM_REG).lo & 0x7; + msr = rdmsr(PSTATE_0_MSR + high_state); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); cpufid = (msr.lo & 0x3f); cpudid = (msr.lo & 0x1c0) >> 6; - return (100 * (cpufid + 0x10)) / (0x01 << cpudid); + mhz = (100 * (cpufid + 0x10)) / (0x01 << cpudid); + return mhz; } |